WO2014174573A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
WO2014174573A1
WO2014174573A1 PCT/JP2013/061787 JP2013061787W WO2014174573A1 WO 2014174573 A1 WO2014174573 A1 WO 2014174573A1 JP 2013061787 W JP2013061787 W JP 2013061787W WO 2014174573 A1 WO2014174573 A1 WO 2014174573A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
semiconductor device
lead frame
seating surfaces
resin
Prior art date
Application number
PCT/JP2013/061787
Other languages
English (en)
French (fr)
Inventor
威宏 國光
田中　大輔
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to EP13882841.3A priority Critical patent/EP2991108A4/en
Priority to PCT/JP2013/061787 priority patent/WO2014174573A1/ja
Priority to JP2015513380A priority patent/JPWO2014174573A1/ja
Priority to US14/650,191 priority patent/US20150318247A1/en
Priority to CN201380075828.7A priority patent/CN105144376A/zh
Publication of WO2014174573A1 publication Critical patent/WO2014174573A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101—Structure
    • H01L2224/4103—Connectors having different sizes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device in which an electronic component is mounted on a lead frame and resin-sealed, and a manufacturing method thereof.
  • a lead frame as a wiring member has a plurality of electrically independent seating surfaces, and electronic components are mounted so as to bridge the two seating surfaces.
  • a component is sealed with a mold resin (Patent Document 1).
  • stress is applied to the electronic component mounted so as to bridge the two electrically independent seating surfaces of the lead frame, and peeling or cracking of the electrode of the electronic component occurs.
  • the stress applied to the electronic component is the stress due to the step generated between the two seating surfaces, the stress due to the pressure of the resin when sealed with the mold resin, or the stress due to the heat from the heating element mounted on the lead frame, etc. There are various factors.
  • the present invention prevents the electronic component from being damaged by stress applied to the electronic component mounted so as to bridge two electrically independent seating surfaces of the lead frame, and has durability.
  • An object of the present invention is to obtain an excellent semiconductor device. It is another object of the present invention to provide a method of manufacturing a semiconductor device that can relieve stress applied to an electronic component mounted so as to bridge two seating surfaces.
  • a semiconductor device includes a lead frame having a plurality of electrically independent seating surfaces, an electronic component mounted on the seating surface via a conductive bonding material, and a mold for sealing the lead frame and the electronic component.
  • a semiconductor device including a resin wherein the electronic component includes a first electronic component mounted so as to bridge two seating surfaces, and the first electronic component includes a resin electrode. Is.
  • the method of manufacturing a semiconductor device includes an outer frame, a plurality of electrically independent seating surfaces disposed inside the outer frame, and a plurality of different directions extending from the seating surface to be integrated with the outer frame.
  • a first step of preparing a lead frame having a connected portion, and a second step of mounting the first electronic component so as to bridge the two seating surfaces of the lead frame following the first step Then, following the second step, the lead frame is placed on the pedestal, and each of the two seating surfaces on which the first electronic component is mounted is pressed in the direction of the pedestal with a pressing member, and the lead frame and A third step of sealing the first electronic component with molten mold resin and extracting the presser member before the mold resin is cured, and following the third step, an outer frame and a connecting portion that are unnecessary on the circuit Including a fourth step of cutting A.
  • the resin electrode is peeled off when stress is applied to the first electronic component. By doing so, damage to the component main body can be prevented, and failure of the semiconductor device can be prevented. Therefore, a semiconductor device having excellent durability can be obtained.
  • the lead frame is placed on the base, and the first electronic component is mounted. Since the lead frame and the first electronic component are sealed with the mold resin in a state in which each of the two seating surfaces mounted with is pressed in the direction of the pedestal by the pressing member, the first resin is sealed by the pressure of the mold resin. Electronic components can be prevented from being damaged, and a semiconductor device can be prevented from malfunctioning. Therefore, a semiconductor device having excellent durability can be manufactured.
  • 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention.
  • 1 is a top view showing an internal configuration of a semiconductor device according to a first embodiment of the present invention. It is a top view which shows the lead frame which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the resin electrode capacitor used for the semiconductor device which concerns on Embodiment 1 of this invention. It is a top view explaining the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a fragmentary sectional view explaining the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a top view explaining the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 1 is a partial cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a circuit diagram of the semiconductor device according to the first embodiment, and shows one phase of a three-phase bridge circuit constituting a motor drive circuit.
  • 2 shows the internal configuration of the semiconductor device according to the first embodiment of the present invention
  • FIG. 3 shows the lead frame before the electronic components of the semiconductor device according to the first embodiment are mounted. Yes.
  • the same reference numerals are given to the same portions in the drawings.
  • the semiconductor device 1 includes a power semiconductor chip 31 as a switching element that constitutes an upper arm for outputting alternating current from direct current, and a power as a switching element that constitutes a lower arm.
  • FETs are used as the power semiconductor chips 31 and 32 constituting the upper and lower arms.
  • the chip capacitor 35 for example, a ceramic capacitor is used.
  • the relay semiconductor chip 33 is inserted between the output terminal of the semiconductor device 1 and the output terminal of the bridge circuit, and connects or blocks the output of the semiconductor device 1.
  • the shunt resistor 34 is inserted between the lower arm and GND, and the chip capacitor 35 is inserted between the external power supply and GND.
  • the lead frame constituting the semiconductor device 1 according to the first embodiment is press-cut into a state as shown in FIG.
  • the lead frame 2 shown in FIG. 3 has a plurality of electrically independent seating surfaces 21, 22, 23, 24a and 24b, and electronic components are mounted on these seating surfaces.
  • the seat surface 21 is configured with a power terminal portion connected to an external power terminal
  • the seat surface 22 is configured with a power line portion for connection with a motor / power line.
  • the seat surface 23 is configured with a GND portion connected to an external GND.
  • die pad portions that form internal wiring of the semiconductor device 1 are configured.
  • the lead frame 2 includes a signal deriving portion 25 for inputting / outputting signals to / from the outside, an outer frame 26 surrounding the outer periphery, and a beam 27 or a terminal (not shown) that is a connecting portion that connects each seating surface and the outer frame 26. have.
  • the beam 27 is an unnecessary part on the circuit, but is integrated with the outer frame 26 or another beam 27 and supports the respective seating surfaces 21, 22, 23, 24a, 24b.
  • the semiconductor device 1 In the semiconductor device 1 according to the first embodiment, two chip capacitors 35 are mounted so as to bridge the two seating surfaces 21 and 23. As these chip capacitors 35, resin electrodes having resin electrodes are provided. It is characterized by using a capacitor. As shown in FIG. 4, the resin electrode capacitor includes an element base 351 that is a capacitor element, an internal electrode 352, and a resin electrode 353 that is an external electrode.
  • the resin electrode 353 when stress is applied from the outside, the resin electrode 353 is peeled off to prevent damage to the internal electrode 352 and the element base 351 and to avoid destruction of the component main body. Note that since the resin electrode 353 is not completely peeled off from the capacitor element, the operation of the circuit is maintained.
  • one electrode of the chip capacitor 35 is joined to a seating surface 21 on which a power semiconductor chip 31 as a switching element is mounted and connected to an external power supply terminal, and the other electrode is a seating surface 23 that constitutes a GND portion.
  • the chip capacitor 35 is directly mounted so as to bridge the seating surfaces 21 and 23 and is disposed in the vicinity of the switching element, so that switching noise is efficiently removed.
  • a lead frame 2 shown in FIG. 3 is prepared. That is, the outer frame 26, a plurality of electrically independent seating surfaces 21, 22, 23, 24 a, 24 b disposed inside the outer frame 26, and extending from these seating surfaces in different directions, A lead frame 2 having a beam 27 integrated with a frame 26 or another beam 27 is prepared.
  • the two seating surfaces 21 and 23 that are mounted so that the chip capacitor 35 bridges each other have three or more beams 27 extending in different directions, and the outer frame 26 or It is assumed that it is integrated with other beams 27.
  • beams 271, 272, 273, and 274 extend from the seat surface 21.
  • beams 274, 275, and 276 extend from the seat surface.
  • a chip capacitor 35 having a resin electrode is mounted so as to bridge the two seating surfaces 21 and 23.
  • the seating surfaces 21 and 23 are integrated with the outer frame 26 or other beams 27 by three or more beams 27 extending in different directions. The step between the seating surface 21 and the seating surface 23 can be suppressed, and the stress applied to the chip capacitor 35 is relieved by the step.
  • the power semiconductor chip 31 constituting the upper arm is mounted on the seat surface 21 and the power semiconductor chip 32 constituting the lower arm is mounted on the seat surface 24a.
  • the relay semiconductor chip 33 is mounted on the seating surface 22. Subsequently, the power semiconductor chip 31, the relay semiconductor chip 33, and the seating surface 24a which is a die pad part are connected by the power terminal part 4a. Further, the power semiconductor chip 32 mounted on the seating surface 24a and the seating surface 24b, which is a die pad portion on which the shunt resistor 34 is mounted, are connected by the power terminal unit 4b.
  • the shunt resistor 34 is mounted so as to bridge the seating surface 24b and the seating surface 23 constituting the GND portion.
  • the gate of the power semiconductor chip 31, the gate and drain of the power semiconductor chip 32, and the gate and source of the relay semiconductor chip 33 are connected to the signal deriving unit 25 by wire bonding 5.
  • a lead-free solder, a eutectic solder material, a conductive adhesive, or the like can be used as the conductive bonding material 6 (see FIG. 6). Note that the order of mounting these electronic components is not limited.
  • the lead frame 2 is placed on the base 10, and the two seating surfaces 21 and 23 on which the chip capacitors 35 are mounted in the second step are mounted.
  • Each of the provided pressing portions 8a and 8b is pressed in the direction of the base 10 by pins 9a and 9b which are pressing members.
  • the molten mold resin is poured into a mold, and the electronic component including the lead frame 2 on which the electronic component is mounted and the chip capacitor 35 mounted on the surface is sealed with the mold resin 7.
  • the seating surfaces 21 and 23 mounted so that the chip capacitor 35 is bridged are integrated with the outer frame 26 or other beams 27 by three or more beams 27 extending in different directions.
  • the stress applied to the chip capacitor 35 due to the level difference between the seating surfaces 21 and 23 at the time of mounting in the second step, and also in the third step, sealing is performed.
  • the stress applied to the lead frame 2 and the chip capacitor 35 can be relaxed by the pressure of the mold resin 7 at the time of stopping.
  • the seat surfaces 21 and 22 of the lead frame 2 are pressed in the direction of the base 10 with the pins 9 a and 9 b, whereby the mold resin 7
  • the stress applied to the lead frame 2 and the chip capacitor 35 is relieved by this pressure.
  • the resin electrode 353 of the chip capacitor 35 is peeled off, so that the internal electrode 352 and the element base 351 can be prevented from being damaged. A failure of the semiconductor device 1 can be prevented.
  • the shunt resistor 34 and the power terminal portions 4a and 4b are also mounted so as to bridge the two seating surfaces, these element bodies are metal, and the possibility of damage to the main body due to stress is low. For this reason, the seat surface 22 and the seat surfaces 24a and 24b do not have a structure integrated with the outer frame by three or more beams.
  • the surface of the lead frame 2 opposite to the surface on which the electronic components are mounted is exposed from the mold resin 7.
  • the flatness of the lead frame 2 is easily obtained by not sealing the surface of the lead frame 2 on which no electronic components are mounted. Since the mounted electronic component includes a heating element that generates heat, the surface of the lead frame 2 where the electronic component is not mounted, that is, the surface exposed from the mold resin 7 is used as a heat dissipation member such as a heat sink. You may join. Thereby, the thermal stress applied to the lead frame 2 can be relieved and the electronic component and the semiconductor device 1 can be prevented from being damaged.
  • the lead frame 2 having the plurality of electrically independent seating surfaces 21, 22, 23, 24a, and 24b, and the conductive bonding material 6 on these seating surfaces.
  • Chip capacitor mounted so as to bridge the two seating surfaces 21 and 23 in the semiconductor device 1 including the electronic component mounted via the lead frame 2 and the mold resin 7 for sealing the lead frame 2 and the electronic component
  • a resin electrode capacitor having a resin electrode as 35 it is possible to prevent damage to the internal electrode 352 and the element base 351 by peeling off the resin electrode 353 when stress is applied to the chip capacitor 35. 1 failure can be prevented. Therefore, the semiconductor device 1 having excellent durability can be obtained.
  • the chip capacitor 35 is mounted so as to bridge the two seating surfaces 21 and 23 of the lead frame 2 and then sealed with the mold resin 7. At this time, the seat surfaces 21 and 22 are pressed in the direction of the pedestal 10 with the pins 9a and 9b, so that the chip capacitor 35 can be prevented from being damaged by the pressure of the mold resin 7, and the semiconductor device can be damaged. Can be prevented. Therefore, a semiconductor device having excellent durability can be manufactured.
  • the two seat surfaces 21 and 23 of the lead frame 2 mounted so as to bridge the chip capacitor 35 are connected to the outer frame 26 or other beams 27 by three or more beams 27 extending in different directions. Since they are integrated, it is possible to suppress the occurrence of a step between the two seating surfaces 21 and 23 and to relieve the stress applied to the lead frame 2 and the chip capacitor 35 by the pressure of the mold resin 7 at the time of sealing. can do.
  • a resin electrode capacitor has been described as an example of the electronic component mounted so as to bridge the two seating surfaces 21 and 23 of the lead frame 2, but the present invention is not limited thereto. It is not limited.
  • an electronic component having a resin electrode there are a resin electrode resistor, a coil and the like in addition to the resin electrode capacitor, and any of them can be applied to the present invention.
  • the semiconductor device 1 that constitutes the drive circuit that performs motor control has been described as an example.
  • the present invention provides an electronic circuit that bridges two independent seating surfaces of the lead frame.
  • the present invention is applicable to all semiconductor devices in which components are mounted and sealed with mold resin.
  • the embodiments can be appropriately modified and omitted within the scope of the invention.
  • the present invention can be used for a semiconductor device in which electronic components are mounted so as to bridge independent seating surfaces of a lead frame and sealed with a mold resin.

Abstract

　リードフレームの２つの座面（２１、２３）を橋絡するように搭載されたチップコンデンサ（３５）として、樹脂電極を有する樹脂電極コンデンサを用いた。これにより、チップコンデンサ（３５）に座面（２１、２３）の段差による応力や、封止の際のモールド樹脂（７）の圧力による応力が加わった場合に、樹脂電極が剥離することで素子基体の破損を防ぐことができ、半導体装置の故障を防ぐことができる。

Description

半導体装置およびその製造方法
　本発明は、リードフレーム上に電子部品を搭載し樹脂封止してなる半導体装置およびその製造方法に関するものである。
　従来の半導体装置において、配線部材であるリードフレームが電気的に独立した複数の座面を有しており、それら２つの座面を橋絡するように電子部品を搭載し、これらリードフレームおよび電子部品をモールド樹脂により封止したものがある（特許文献１）。
特開２００６―３２７７４号公報
　上記のような構成の半導体装置においては、リードフレームの電気的に独立した２つの座面を橋絡するように搭載された電子部品に応力がかかり、電子部品の電極の剥離やクラックが発生し、半導体装置の故障の原因となっていた。電子部品にかかる応力は、２つの座面の間に生じる段差による応力や、モールド樹脂で封止する際の樹脂の圧力による応力、またはリードフレームに搭載された発熱体からの熱による応力等、様々な要因によるものがある。
　本発明は、上記問題点に鑑み、リードフレームの電気的に独立した２つの座面を橋絡するように搭載される電子部品にかかる応力により該電子部品が破損するのを防止し、耐久性に優れた半導体装置を得ることを目的とする。また、２つの座面を橋絡するように搭載される電子部品にかかる応力を緩和することが可能な半導体装置の製造方法を提供することを目的とする。
　本発明による半導体装置は、電気的に独立した複数の座面を有するリードフレームと、座面上に導電性接合材を介して搭載された電子部品と、リードフレームおよび電子部品を封止するモールド樹脂を備えた半導体装置であって、電子部品は、２つの座面を橋絡するように搭載された第１の電子部品を含み、第１の電子部品は樹脂電極を有することを特徴とするものである。
　また、本発明による半導体装置の製造方法は、外枠と、外枠の内側に配置され電気的に独立した複数の座面と、座面から異なる複数の方向に延出して外枠と一体化された連結部を有するリードフレームを用意する第１の工程と、第１の工程に続いて、リードフレームの２つの座面を橋絡するように第１の電子部品を実装する第２の工程と、第２の工程に続いて、リードフレームを台座に載置し、第１の電子部品が実装された２つの座面のそれぞれを押え部材で台座の方向に押圧した状態で、リードフレームおよび第１の電子部品を溶融したモールド樹脂で封止すると共に、モールド樹脂が硬化する前に押え部材を抜き取る第３の工程と、第３の工程に続いて、回路上不要な外枠及び連結部を切断する第４の工程を含むことを特徴とするものである。
　本発明に係る半導体装置は、２つの座面を橋絡するように搭載された第１の電子部品が樹脂電極を有することにより、第１の電子部品に応力が加わった場合に樹脂電極が剥離することで部品本体の破損を防ぐことができ、半導体装置の故障を防ぐことができる。よって、耐久性に優れた半導体装置が得られる。
　また、本発明に係る半導体装置の製造方法は、リードフレームの２つの座面を橋絡するように第１の電子部品を実装した後、リードフレームを台座に載置し、第１の電子部品が実装された２つの座面のそれぞれを押え部材で台座の方向に押圧した状態でリードフレームおよび第１の電子部品をモールド樹脂で封止するようにしたので、モールド樹脂の圧力によって第１の電子部品が破損するのを防ぐことができ、半導体装置の故障を防ぐことができる。よって、耐久性に優れた半導体装置を製造することができる。
　この発明の上記以外の目的、特徴、観点及び効果は、図面を参照する以下のこの発明の詳細な説明から、さらに明らかになるであろう。
本発明の実施の形態１に係る半導体装置の回路図である。 本発明の実施の形態１に係る半導体装置の内部構成を示す上面図である。 本発明の実施の形態１に係るリードフレームを示す上面図である。 本発明の実施の形態１に係る半導体装置に用いられる樹脂電極コンデンサの構成を示す図である。 本発明の実施の形態１に係る半導体装置の製造方法を説明する上面図である。 本発明の実施の形態１に係る半導体装置の製造方法を説明する部分断面図である。 本発明の実施の形態１に係る半導体装置の製造方法を説明する上面図である。 本発明の実施の形態１に係る半導体装置を示す部分断面図である。
実施の形態１．
　本発明の実施の形態１に係る半導体装置について、図面に基づいて説明する。図１は、本実施の形態１に係る半導体装置の回路図であり、モータ駆動回路を構成する３相ブリッジ回路の１相分を示している。また、図２は、本発明の実施の形態１に係る半導体装置の内部構成を示し、図３は、本実施の形態１に係る半導体装置の電子部品が実装される前のリードフレームを示している。なお、以下のすべての図において、図中、同一部分には同一符号を付している。
　図１および図２に示すように、半導体装置１は、直流から交流を出力するための上段側アームを構成するスイッチング素子としてのパワー半導体チップ３１と、下段側アームを構成するスイッチング素子としてのパワー半導体チップ３２と、リレー機能を有したスイッチング素子としてのリレー半導体チップ３３と、モータ電流をモニタするためのシャント抵抗３４と、ノイズを抑制するスナバコンデンサとしての２個のチップコンデンサ（第１の電子部品）３５を備えている。上下アームを構成するパワー半導体チップ３１、３２としては、例えばＦＥＴが用いられる。また、チップコンデンサ３５としては、例えばセラミックコンデンサが用いられる。
　リレー半導体チップ３３は、半導体装置１の出力端子とブリッジ回路の出力端子との間に挿入され、半導体装置１の出力を接続または遮断する。シャント抵抗３４は、下段側アームとＧＮＤとの間に挿入され、チップコンデンサ３５は、外部の電源とＧＮＤとの間に挿入される。これらの電子部品は、高導電且つ高熱伝導である銅製のリードフレームの座面上に導電性接合材を介して搭載され、モールド樹脂により封止される。
　本実施の形態１に係る半導体装置１を構成するリードフレームは、図３に示すような状態にプレスカットされる。図３に示すリードフレーム２は、電気的に独立した複数の座面２１、２２、２３、２４ａ、２４ｂを有しており、これらの座面に電子部品が搭載される。座面２１には、外部の電源端子と接続される電源端子部が構成され、座面２２には、モータ・パワーラインと接続するためのパワーライン部が構成される。また、座面２３には、外部のＧＮＤと接続されるＧＮＤ部が構成される。座面２４ａ、２４ｂには、半導体装置１の内部配線を形成するダイパッド部が構成される。
　さらに、リードフレーム２は、外部と信号を入出力するシグナル導出部２５と、外周を囲む外枠２６と、各座面と外枠２６を繋ぐ連結部であるはり２７または端子（図示せず）を有している。はり２７は回路上不要な部位であるが、外枠２６または他のはり２７と一体化され、各座面２１、２２、２３、２４ａ、２４ｂを支持している。
　本実施の形態１に係る半導体装置１においては、２つの座面２１、２３を橋絡するように２つのチップコンデンサ３５が搭載されるが、これらのチップコンデンサ３５として、樹脂電極を有する樹脂電極コンデンサを用いることを特徴としている。樹脂電極コンデンサは、図４に示すように、コンデンサ素子である素子基体３５１と内部電極３５２、および外部電極となる樹脂電極３５３から構成される。
　樹脂電極コンデンサは、外部から応力が加わった場合、樹脂電極３５３が剥離することで内部電極３５２および素子基体３５１の損傷を防ぎ、部品本体の破壊を回避する。なお、樹脂電極３５３は、コンデンサ素子から完全には剥がれないため、回路の動作は保たれる。
　また、チップコンデンサ３５の一方の電極は、スイッチング素子であるパワー半導体チップ３１が搭載され外部の電源端子と接続される座面２１に接合され、他方の電極はＧＮＤ部が構成される座面２３に接合される。このように、チップコンデンサ３５を、座面２１、２３に橋絡するように直接実装し、スイッチング素子の近傍に配置することで、スイッチングノイズを効率的に除去するものである。
　本実施の形態１に係る半導体装置の製造方法について説明する。まず、第１の工程として、図３に示すリードフレーム２を用意する。すなわち、外枠２６と、外枠２６の内側に配置され電気的に独立した複数の座面２１、２２、２３、２４ａ、２４ｂと、それらの座面から異なる複数の方向に延出して、外枠２６または他のはり２７と一体化されたはり２７を有するリードフレーム２を用意する。
　なお、複数の座面のうち、チップコンデンサ３５が橋絡するように搭載される２つの座面２１、２３はいずれも、３本以上のはり２７がそれぞれ異なる方向に延出して外枠２６または他のはり２７と一体化されたものとする。具体的には、座面２１からは、はり２７１、２７２、２７３、２７４が延出している。また、座面２３からは、はり２７４、２７５、２７６が延出している。
　続いて、第２の工程として、図５に示すように、リードフレーム２の各座面上に、電子部品を実装する。具体的には、樹脂電極を有するチップコンデンサ３５を、２つの座面２１、２３を橋絡するように実装する。前述のように、座面２１、２３は、それぞれ異なる方向に延出した３本以上のはり２７により外枠２６または他のはり２７と一体化されているため、チップコンデンサ３５を実装する際に、座面２１と座面２３の間の段差を抑制することができ、段差によりチップコンデンサ３５にかかる応力が緩和される。
　また、上段側アームを構成するパワー半導体チップ３１を座面２１に、下段側アームを構成するパワー半導体チップ３２を座面２４ａに実装する。同様に、リレー半導体チップ３３を座面２２に実装する。続いて、パワー半導体チップ３１とリレー半導体チップ３３、およびダイパッド部である座面２４ａを、パワー・ターミナル部４ａで接続する。また、座面２４ａに実装されたパワー半導体チップ３２と、シャント抵抗３４が実装されたダイパッド部である座面２４ｂを、パワー・ターミナル部４ｂで接続する。シャント抵抗３４は、座面２４ｂと、ＧＮＤ部を構成する座面２３を橋絡するように実装される。
　さらに、パワー半導体チップ３１のゲート、パワー半導体チップ３２のゲートとドレイン、リレー半導体チップ３３のゲートとソースを、ワイヤーボンディング５によりシグナル導出部２５に接続する。これらの電子部品の実装には、導電性接合材６（図６参照）として鉛フリー半田や共晶半田材、または導電性接着剤等を用いることができる。なお、これらの電子部品を実装する順序は、限定されるものではない。
　続いて、第３の工程として、図６および図７に示すように、リードフレーム２を台座１０に載置し、第２の工程でチップコンデンサ３５が実装された２つの座面２１、２３に設けられた押え部８ａ、８ｂのそれぞれを、押え部材であるピン９ａ、９ｂで台座１０の方向に押圧する。この状態で、溶融したモールド樹脂を型に流し込み、リードフレーム２の電子部品が搭載された面側、およびその面に搭載されたチップコンデンサ３５を含む電子部品をモールド樹脂７で封止する。
　モールド樹脂７で封止することにより、モールド樹脂７の熱伝導によってモジュール内部の熱的均衡が図られ、リードフレーム２にかかる熱応力が緩和され、電子部品にかかる応力が緩和される。なお、ピン９ａ、９ｂは、モールド樹脂７が硬化する前に抜き取られるため、図８に示すように、完成した半導体装置１のモールド樹脂７には、ピン９ａ、９ｂが抜き取られた跡の穴は残らない。
　前述のように、チップコンデンサ３５が橋絡するように実装された座面２１、２３は、それぞれ異なる方向に延出した３本以上のはり２７により、外枠２６または他のはり２７と一体化されている。このような構造をとることにより、第２の工程での実装時の座面２１、２３の段差によりチップコンデンサ３５にかかる応力を抑制することができ、さらに、この第３の工程においても、封止時のモールド樹脂７の圧力によりリードフレーム２およびチップコンデンサ３５にかかる応力を緩和することができる。
　また、第３の工程においては、溶融したモールド樹脂７で封止する際に、リードフレーム２の座面２１、２２を、ピン９ａ、９ｂで台座１０の方向に押圧することにより、モールド樹脂７の圧力によってリードフレーム２およびチップコンデンサ３５にかかる応力を緩和している。さらに、封止の際のモールド樹脂７の圧力によってチップコンデンサ３５に応力がかかっても、チップコンデンサ３５の樹脂電極３５３が剥離することで内部電極３５２および素子基体３５１の破損を防ぐことができ、半導体装置１の故障を防ぐことができる。
　なお、シャント抵抗３４およびパワー・ターミナル部４ａ、４ｂも、２つの座面を橋絡するように実装されるが、これらの素体は金属であり、応力による本体破損の可能性は低い。このため、座面２２及び座面２４ａ、２４ｂは、３本以上のはりによって外枠と一体化される構造をとっていない。
　続いて、第４の工程として、リードフレーム２の回路上不要な外枠２６及びはり２７を切断する。
　以上、第１の工程から第４の工程を経て製造された半導体装置１は、リードフレーム２の電子部品が搭載された面と反対側の面がモールド樹脂７より露出している。このように、リードフレーム２の電子部品が搭載されていない面を樹脂封止しないことにより、リードフレーム２の平面度が出しやすい。また、搭載されている電子部品は、発熱を伴う発熱体を含むため、リードフレーム２の電子部品が搭載されていない面、すなわちモールド樹脂７から露出している面を、ヒートシンク等の放熱部材に接合してもよい。これにより、リードフレーム２にかかる熱応力を緩和し、電子部品および半導体装置１の破損を防ぐことができる。
　以上のように、本実施の形態１によれば、電気的に独立した複数の座面２１、２２、２３、２４ａ、２４ｂを有するリードフレーム２と、これらの座面上に導電性接合材６を介して搭載された電子部品と、これらリードフレーム２および電子部品を封止するモールド樹脂７を備えた半導体装置１において、２つの座面２１、２３を橋絡するように搭載されるチップコンデンサ３５として、樹脂電極を有する樹脂電極コンデンサを用いることにより、チップコンデンサ３５に応力が加わった場合に樹脂電極３５３が剥離することで内部電極３５２および素子基体３５１の破損を防ぐことができ、半導体装置１の故障を防ぐことができる。よって、耐久性に優れた半導体装置１が得られる。
　また、本実施の形態１に係る半導体装置の製造方法によれば、リードフレーム２の２つの座面２１、２３を橋絡するようにチップコンデンサ３５を実装した後、モールド樹脂７で封止する際に、座面２１、２２をピン９ａ、９ｂで台座１０の方向に押圧するようにしたので、モールド樹脂７の圧力によってチップコンデンサ３５が破損するのを防ぐことができ、半導体装置の故障を防ぐことができる。よって、耐久性に優れた半導体装置を製造することができる。
　また、チップコンデンサ３５が橋絡するように搭載されるリードフレーム２の２つの座面２１、２３を、それぞれ異なる方向に延出した３本以上のはり２７により外枠２６または他のはり２７と一体化したので、２つの座面２１、２３の間に段差が生じるのを抑制することができると共に、封止の際のモールド樹脂７の圧力によりリードフレーム２およびチップコンデンサ３５にかかる応力を緩和することができる。
　なお、本実施の形態１では、リードフレーム２の２つの座面２１、２３を橋絡するように搭載される電子部品として、樹脂電極コンデンサを例に挙げて説明したが、本発明はこれに限定されるものではない。樹脂電極を有する電子部品としては、樹脂電極コンデンサの他に、樹脂電極抵抗やコイル等があり、いずれも本発明に適用可能である。
　また、本実施の形態１では、モータ制御を行う駆動回路を構成する半導体装置１を例に挙げて説明したが、本発明は、リードフレームの独立した２つの座面を橋絡するように電子部品を搭載し、モールド樹脂で封止してなる半導体装置全般について適用可能なものである。なお、本発明は、その発明の範囲内において、実施の形態を適宜、変形、省略することが可能である。
　本発明は、リードフレームの独立した座面を橋絡するように電子部品を搭載し、モールド樹脂で封止してなる半導体装置に利用することができる。

Claims (7)

  1. 　電気的に独立した複数の座面を有するリードフレーム、前記座面上に導電性接合材を介して搭載された電子部品、前記リードフレームおよび前記電子部品を封止するモールド樹脂を備えた半導体装置であって、
    前記電子部品は、２つの前記座面を橋絡するように搭載された第１の電子部品を含み、前記第１の電子部品は樹脂電極を有することを特徴とする半導体装置。
  2. 　前記電子部品はスイッチング素子を含み、前記第１の電子部品はコンデンサであり、前記コンデンサの一方の前記樹脂電極は、前記スイッチング素子が搭載された前記座面に接合されることを特徴とする請求項１記載の半導体装置。
  3. 　前記リードフレームの前記電子部品が搭載された面と反対側の面は、前記モールド樹脂より露出していることを特徴とする請求項１または請求項２に記載の半導体装置。
  4. 　前記リードフレームの前記電子部品が搭載された面と反対側の面は、放熱部材に接合されることを特徴とする請求項３記載の半導体装置。
  5. 　外枠と、前記外枠の内側に配置され電気的に独立した複数の座面と、前記座面から異なる複数の方向に延出して前記外枠と一体化された連結部を有するリードフレームを用意する第１の工程、
    前記第１の工程に続いて、前記リードフレームの２つの前記座面を橋絡するように第１の電子部品を実装する第２の工程、
    前記第２の工程に続いて、前記リードフレームを台座に載置し、前記第１の電子部品が実装された前記２つの座面のそれぞれを押え部材で前記台座の方向に押圧した状態で、前記リードフレームおよび前記第１の電子部品を溶融したモールド樹脂で封止すると共に、前記モールド樹脂が硬化する前に前記押え部材を抜き取る第３の工程、
    前記第３の工程に続いて、回路上不要な前記外枠及び前記連結部を切断する第４の工程を含むことを特徴とする半導体装置の製造方法。
  6. 　前記第２の工程において実装される前記第１の電子部品は、樹脂電極を有することを特徴とする請求項５記載の半導体装置の製造方法。
  7. 　前記第２の工程において前記第１の電子部品が実装される前記２つの座面はいずれも、３本以上の前記連結部がそれぞれ異なる方向に延出して前記外枠または他の前記連結部と一体化されていることを特徴とする請求項５または請求項６に記載の半導体装置の製造方法。
PCT/JP2013/061787 2013-04-22 2013-04-22 半導体装置およびその製造方法 WO2014174573A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP13882841.3A EP2991108A4 (en) 2013-04-22 2013-04-22 Semiconductor device and method of manufacture thereof
PCT/JP2013/061787 WO2014174573A1 (ja) 2013-04-22 2013-04-22 半導体装置およびその製造方法
JP2015513380A JPWO2014174573A1 (ja) 2013-04-22 2013-04-22 半導体装置およびその製造方法
US14/650,191 US20150318247A1 (en) 2013-04-22 2013-04-22 Semiconductor device and manufacturing method of the same
CN201380075828.7A CN105144376A (zh) 2013-04-22 2013-04-22 半导体装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/061787 WO2014174573A1 (ja) 2013-04-22 2013-04-22 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
WO2014174573A1 true WO2014174573A1 (ja) 2014-10-30

Family

ID=51791184

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/061787 WO2014174573A1 (ja) 2013-04-22 2013-04-22 半導体装置およびその製造方法

Country Status (5)

Country Link
US (1) US20150318247A1 (ja)
EP (1) EP2991108A4 (ja)
JP (1) JPWO2014174573A1 (ja)
CN (1) CN105144376A (ja)
WO (1) WO2014174573A1 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016125673A1 (ja) * 2015-02-02 2016-08-11 株式会社村田製作所 半導体モジュールおよびパワーコントロールユニット
WO2017154232A1 (ja) * 2016-03-11 2017-09-14 新電元工業株式会社 半導体装置及びリードフレーム
WO2017154198A1 (ja) * 2016-03-11 2017-09-14 新電元工業株式会社 半導体装置及びその製造方法、リードフレーム
JP2018060902A (ja) * 2016-10-05 2018-04-12 三菱電機株式会社 モールド樹脂封止型パワー半導体装置
JP6373468B1 (ja) * 2017-10-19 2018-08-15 三菱電機株式会社 パワーモジュール
WO2019077874A1 (ja) * 2017-10-19 2019-04-25 株式会社デンソー リードフレーム

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017147272A (ja) 2016-02-15 2017-08-24 ローム株式会社 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体
CN105764191A (zh) * 2016-03-31 2016-07-13 中山市高乐电子科技有限公司 一种散热性好的led驱动装置
US10365303B2 (en) * 2016-04-28 2019-07-30 Texas Instruments Incorporated Shunt strip
CN108447682A (zh) * 2018-04-16 2018-08-24 南京幕府信息技术有限公司 一种抗压式贴片电容
JP7134137B2 (ja) * 2019-05-31 2022-09-09 三菱電機株式会社 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676502A (en) * 1979-11-28 1981-06-24 Nippon Electric Co Method of forming external electrode for electronic part
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
JPH10335358A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置の製造方法
JP2004172402A (ja) * 2002-11-20 2004-06-17 Shindengen Electric Mfg Co Ltd 半導体装置
JP2006032774A (ja) 2004-07-20 2006-02-02 Denso Corp 電子装置
JP2009129952A (ja) * 2007-11-20 2009-06-11 Denso Corp 半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275602A (ja) * 1992-03-27 1993-10-22 Omron Corp 電子機器
JP2000003923A (ja) * 1998-06-16 2000-01-07 Hitachi Ltd 半導体装置の樹脂封止方法及びその樹脂封止装置
JP2000138130A (ja) * 1998-11-02 2000-05-16 Kyocera Corp チップ型電子部品
JP2002110867A (ja) * 2000-10-02 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
JP4052111B2 (ja) * 2002-06-07 2008-02-27 ソニー株式会社 無線情報記憶媒体
JP2004152994A (ja) * 2002-10-30 2004-05-27 Renesas Technology Corp 半導体装置の樹脂封止装置及び半導体装置の製造方法
JP4844311B2 (ja) * 2006-09-14 2011-12-28 株式会社村田製作所 セラミック電子部品
JP4803451B2 (ja) * 2006-12-26 2011-10-26 Ｔｄｋ株式会社 電子部品及びその実装構造
US20110231637A1 (en) * 2009-09-21 2011-09-22 Ocz Technology Group, Inc. Central processing unit and method for workload dependent optimization thereof
JP5278709B2 (ja) * 2009-12-04 2013-09-04 株式会社村田製作所 導電性樹脂組成物およびチップ型電子部品
JP5099243B2 (ja) * 2010-04-14 2012-12-19 株式会社デンソー 半導体モジュール
JP2012104785A (ja) * 2010-11-15 2012-05-31 Tdk Corp チップ型電子部品の実装構造、チップ型電子部品の実装方法、チップ型電子部品、及びチップ型電子部品の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676502A (en) * 1979-11-28 1981-06-24 Nippon Electric Co Method of forming external electrode for electronic part
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
JPH10335358A (ja) * 1997-05-30 1998-12-18 Nec Corp 半導体装置の製造方法
JP2004172402A (ja) * 2002-11-20 2004-06-17 Shindengen Electric Mfg Co Ltd 半導体装置
JP2006032774A (ja) 2004-07-20 2006-02-02 Denso Corp 電子装置
JP2009129952A (ja) * 2007-11-20 2009-06-11 Denso Corp 半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2991108A4

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2016125673A1 (ja) * 2015-02-02 2017-11-09 株式会社村田製作所 半導体モジュールおよびパワーコントロールユニット
WO2016125673A1 (ja) * 2015-02-02 2016-08-11 株式会社村田製作所 半導体モジュールおよびパワーコントロールユニット
US10438872B2 (en) 2016-03-11 2019-10-08 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and lead frame
WO2017154232A1 (ja) * 2016-03-11 2017-09-14 新電元工業株式会社 半導体装置及びリードフレーム
WO2017154199A1 (ja) * 2016-03-11 2017-09-14 新電元工業株式会社 半導体装置及びリードフレーム
WO2017154198A1 (ja) * 2016-03-11 2017-09-14 新電元工業株式会社 半導体装置及びその製造方法、リードフレーム
CN107534025A (zh) * 2016-03-11 2018-01-02 新电元工业株式会社 半导体装置及其制造方法、引线框
JP6275292B1 (ja) * 2016-03-11 2018-02-07 新電元工業株式会社 半導体装置及びその製造方法
JP6277292B1 (ja) * 2016-03-11 2018-02-07 新電元工業株式会社 半導体装置及びリードフレーム
CN107534025B (zh) * 2016-03-11 2020-03-17 新电元工业株式会社 半导体装置及其制造方法、引线框
US10490490B2 (en) 2016-03-11 2019-11-26 Shindengen Electric Manufacturing Co., Ltd. Thermally conductive semiconductor device and manufacturing method thereof
JP2018060902A (ja) * 2016-10-05 2018-04-12 三菱電機株式会社 モールド樹脂封止型パワー半導体装置
US10242930B2 (en) 2016-10-05 2019-03-26 Mitsubishi Electric Corporation Molded resin-sealed power semiconductor device
JP2019075524A (ja) * 2017-10-19 2019-05-16 株式会社デンソー リードフレーム
JP2019075519A (ja) * 2017-10-19 2019-05-16 三菱電機株式会社 パワーモジュール
WO2019077874A1 (ja) * 2017-10-19 2019-04-25 株式会社デンソー リードフレーム
JP6373468B1 (ja) * 2017-10-19 2018-08-15 三菱電機株式会社 パワーモジュール
JP7006120B2 (ja) 2017-10-19 2022-01-24 株式会社デンソー リードフレーム

Also Published As

Publication number Publication date
US20150318247A1 (en) 2015-11-05
EP2991108A1 (en) 2016-03-02
EP2991108A4 (en) 2017-04-12
JPWO2014174573A1 (ja) 2017-02-23
CN105144376A (zh) 2015-12-09

Similar Documents

Publication Publication Date Title
WO2014174573A1 (ja) 半導体装置およびその製造方法
JP4438489B2 (ja) 半導体装置
JP6319137B2 (ja) 半導体装置及びその製造方法
JP2013026627A (ja) パワー素子パッケージモジュール及びその製造方法
JP5930980B2 (ja) 半導体装置およびその製造方法
US20150235929A1 (en) Electronic device with heat dissipater
JP6813259B2 (ja) 半導体装置
JP5267021B2 (ja) 半導体装置およびそれを用いたインバータ回路
US9871025B2 (en) Commutation cell
JP2003273319A (ja) 両面電極半導体素子を有する電子回路装置及び該電子回路装置の製造方法
JP2014187264A (ja) 半導体装置
JP2017135183A (ja) 半導体装置
JP2004221381A (ja) 半導体装置
JPWO2015145752A1 (ja) 半導体モジュールおよび半導体モジュールを搭載した駆動装置
JP6347323B2 (ja) 半導体装置
US9397053B2 (en) Molded device with anti-delamination structure providing multi-layered compression forces
JP6907670B2 (ja) 半導体装置および半導体装置の製造方法
WO2015052880A1 (ja) 半導体装置及びその製造方法
JP6272573B2 (ja) 電力用半導体装置
JP2004048084A (ja) 半導体パワーモジュール
JP2016004792A (ja) 半導体装置とその製造方法および機器
JP7142714B2 (ja) 電力用半導体装置の製造方法
JP4283137B2 (ja) 半導体装置
JP2023074122A (ja) 電力用半導体装置
JP2005150602A (ja) 半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201380075828.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13882841

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2015513380

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 14650191

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2013882841

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE