KR960039309A - 반도체 장치 및 반도체 칩 설치 방법 - Google Patents
반도체 장치 및 반도체 칩 설치 방법 Download PDFInfo
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- KR960039309A KR960039309A KR1019960014141A KR19960014141A KR960039309A KR 960039309 A KR960039309 A KR 960039309A KR 1019960014141 A KR1019960014141 A KR 1019960014141A KR 19960014141 A KR19960014141 A KR 19960014141A KR 960039309 A KR960039309 A KR 960039309A
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Abstract
반도체 장치는 전극 패드를 갖는 반도체 칩과, 다수의 절연막으로 구성되어 접착제에 의해 반도체 칩에 부착되는 패키지를 포함한다. 패키지는 다수의 절연막 사이에 놓인 배선 패턴을 포함하며, 배선 패턴은 반도체 칩의 사용 목적에 따라 다수 절연막에 제공된 경유구멍을 통하여 전극 패트 및/또는 다른 배선 패턴에 선택적으로 접속된다. 반도체 장치는 또한 최외각 절연막에 제공된 경유구멍을 통하여 최외각 배선 패턴으로부터 확장하는 다수의 전도성 돌출부를 포함한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따라 반도체 칩이 반도체 패키지상에 설치된 반도체 장치의 도식적 구성을 설명하는 단면도.
Claims (22)
- 반도체 장치에 있어서: 전극 패드를 갖는 반도체 칩과; 다수의 절연막으로 구성되어 접착제에 의해 상기 반도체칩에 부착되는 패키지로서, 상기 패키지는 상기 다수의 절연막 사이에 놓인 배선 패턴을 포함하며, 상기 배선 패턴은 상기 반도체 칩의 사용 목적에 따라 상기 다수의 절연막에 제공된 경유구멍을 통하여 상기 전극 패드 및/또는 상기 배선 패턴과는 다른 배선 패턴에 선택적으로 연결되는, 상기 패키지; 및 최외각 절연막에 제공된 경유구멍을 통해 최외각 배선 패턴으로부터 확장되어 있는 다수의 전도성 돌출부를 구비하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 패키지는 상기 반도체 칩과 실질적으로 동일한 영역을 갖는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 배선 패턴은 상기 다수의 절연막중 인접하는 두 절연막 사이의 상기 배선 패턴과는 다른 패턴 전반으로 확장되어 있는 그라운드 라인 배선 패턴을 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항 내지 제3항중 어느 한 항에 있어서, 상기 다수의 전도성 돌출부는 최외각 절연막상에 위치된 확장 랜드 부분으로부터 확장되어 있는 것을 특징으로 하는 반도체 장치.
- 제4항에 있어서, 상기 각각의 확장 랜드 부분은 상기 최외각 절연막에 제공된 경유구멍보다 영역에 있어 큰 것을 특징으로 하는 반도체 장치.
- 제4항에 있어서, 상기 각각의 확장 랜드 부분은 반구 형태를 갖는 것을 특징으로 하는 반도체 장치.
- 제1항 내지 제3항중 어느 한 항에 있어서, 상기 다수의 전도성 돌출부를 에워싸며, 상기 최외각 절연막을 덮고 있는 수지층을 더 구비하는 것을 특징으로 하는 반도체 장치.
- 제7항에 있어서, 상기 수지층은 접착 성질을 가지므로, 상기 반도체 장치는 또다른 기판에 부착되는 것을 특징으로 하는 반도체 장치.
- 제7항에 있어서, 상기 수지층의 물질은 상기 다수의 전도성 돌출부와 같거나 높은 녹는점을 갖는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 상기 다수의 전도성 돌출부는 최외각 절연막상에 위치된 확장 랜드 부분으로부터 확장되는 것을 특징으로 하는 반도체 장치.
- 제10항에 있어서, 상기 각각의 확장 랜드 부분은 상기 최외각 절연막에 제공된 경유구멍보다 영역에 있는 큰 것을 특징으로 하는 반도체 장치.
- 제10항에 있어서, 상기 각각의 확장 랜드 부분은 반구 형태를 갖는 것을 특징으로 하는 반도체 장치.
- 제10항 내지 제12항중 어느 한 항에 있어서, 상기 다수의 전도성 돌출부를 에워싸며, 상기 최외각 절연막을 덮고 있는 수지층을 더 구비하는 것을 특징으로 하는 반도체 장치.
- 제13항에 있어서, 상기 수지층은 접착 성질을 가지므로, 상기 반도체 장치는 또다른 기판에 부착되는 것을 특징으로 하는 반도체 장치.
- 제13항에 있어서, 상기 수지층의 물질은 상기 다수의 전도성 돌출부와 같거나 높은 녹는점을 갖는 것을 특징으로 하는 반도체 장치.
- 반도체 장치를 사용하는 장치 제조 방법에 있어서; 전극 패드를 갖는 반도체 칩과 다수의 절연막으로 구성된 패키지를 제공하는 단계로서, 상기 패키지는 상기 다수의 절연막 사이에 놓인 배선 패턴을 포함하며, 상기 배선 패턴은 상기 반도체 칩의 사용 목적에 따라 상기 다수의 절연막에 제공된 경유구멍을 통하여 상기 전극 패드 및/또는 상기 배선 패턴과는 다른 배선 패턴에 선택적으로 접속되는, 상기 단계와; 접착제에 의해 상기 패키지를 상기 반도체 칩에 부착시키는 단계; 및 반도체 장치를 제조하도록 최외각 절연막에 제공된 경유 구멍을 통하여 최외각 배선 패턴으로부터 확장된 다수의 전도성 돌출부를 형성하는 단계를 구비하는 것을 특징으로 하는 제조방법.
- 제16항에 있어서, 상기 반도체 칩 및 패키지 제공 단계는 상기 다수의 절연막중 인접하는 두 절연막 사이의 상기 배선 패턴과는 다른 배선 전반에 확장하는 그라운드 라인 배선 패턴을 포함하는 상기 패키지를 제공하는 단계를 포함하는 것을 특징으로 하는 제조 방법.
- 제16항에 있어서, 상기 반도체 칩 및 패키지 제공 단계는 상기 다수의 전도성 돌출부에 대해 확장된 랜드 부분을 포함하는 상기 패키지를 제공하는 단계를 포함하며, 상기 확장 랜드 부분은 최외각 절연막에 형성된 경유구멍을 통하여 최외각 배선 패턴에 접속되고 상기 경유구멍 보다도 큰 영역을 갖게 되는 것을 특징으로 하는 제조 방법.
- 제16항에 있어서, 상기 다수의 전도성 돌출부를 에워싸며, 상기 최외각 절연막을 덮고 있는 수지층을 형성하는 단계를 더 구비하는 것을 특징으로 하는 제조 방법.
- 제19항에 있어서, 반도체 장치를 시험하는 단계; 및 인쇄 회로 기판상에 반도체 장치를 설치하는 단계를 더 구비하는 것을 특징으로 하는 제조 방법.
- 제20항에 있어서, 상기 시험 단계는 그 각각이 상기 다수의 전도성 돌출부보다 작은 다수의 돌출 전극을 갖는 시험 탐침을 사용하여 상기 반도체 장치를 시험하는 단계를 포함하는 것을 특징으로 하는 제조 방법.
- 제20항에 있어서, 상기 설치 단계는 상기 다수의 돌출부 및 상기 수지층을 용해함으로써, 상기 반도체 장치를 상기 인쇄 회로 기판에 부착하는 단계를 포함하며, 상기 수지층의 물질은 상기 다수의 전도성 돌출부보다 높거나 같은 녹는점을 갖는 것을 특징으로 하는 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7103812A JP2763020B2 (ja) | 1995-04-27 | 1995-04-27 | 半導体パッケージ及び半導体装置 |
JP95-103812 | 1995-04-27 |
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KR960039309A true KR960039309A (ko) | 1996-11-25 |
KR100248682B1 KR100248682B1 (ko) | 2000-03-15 |
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KR1019960014141A KR100248682B1 (ko) | 1995-04-27 | 1996-04-27 | 반도체 장치 및 반도체 칩 설치 방법 |
Country Status (3)
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US (1) | US5757078A (ko) |
JP (1) | JP2763020B2 (ko) |
KR (1) | KR100248682B1 (ko) |
Families Citing this family (84)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6111317A (en) * | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
JP3376203B2 (ja) | 1996-02-28 | 2003-02-10 | 株式会社東芝 | 半導体装置とその製造方法及びこの半導体装置を用いた実装構造体とその製造方法 |
US5891795A (en) * | 1996-03-18 | 1999-04-06 | Motorola, Inc. | High density interconnect substrate |
US5789271A (en) * | 1996-03-18 | 1998-08-04 | Micron Technology, Inc. | Method for fabricating microbump interconnect for bare semiconductor dice |
US20040061220A1 (en) * | 1996-03-22 | 2004-04-01 | Chuichi Miyazaki | Semiconductor device and manufacturing method thereof |
JP2891665B2 (ja) | 1996-03-22 | 1999-05-17 | 株式会社日立製作所 | 半導体集積回路装置およびその製造方法 |
JPH09312374A (ja) | 1996-05-24 | 1997-12-02 | Sony Corp | 半導体パッケージ及びその製造方法 |
KR100186333B1 (ko) * | 1996-06-20 | 1999-03-20 | 문정환 | 칩 사이즈 반도체 패키지 및 그 제조방법 |
JP2825083B2 (ja) * | 1996-08-20 | 1998-11-18 | 日本電気株式会社 | 半導体素子の実装構造 |
JPH10135270A (ja) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | 半導体装置及びその製造方法 |
JP3695893B2 (ja) * | 1996-12-03 | 2005-09-14 | 沖電気工業株式会社 | 半導体装置とその製造方法および実装方法 |
JPH10178145A (ja) * | 1996-12-19 | 1998-06-30 | Texas Instr Japan Ltd | 半導体装置及びその製造方法並びに半導体装置用絶縁基板 |
US6097098A (en) | 1997-02-14 | 2000-08-01 | Micron Technology, Inc. | Die interconnections using intermediate connection elements secured to the die face |
JP4159631B2 (ja) * | 1997-06-23 | 2008-10-01 | シチズンホールディングス株式会社 | 半導体パッケージの製造方法 |
US6441473B1 (en) * | 1997-09-12 | 2002-08-27 | Agere Systems Guardian Corp. | Flip chip semiconductor device |
US6028354A (en) * | 1997-10-14 | 2000-02-22 | Amkor Technology, Inc. | Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package |
EP1030365A4 (en) | 1997-10-17 | 2007-05-09 | Ibiden Co Ltd | SUBSTRATE OF A HOUSING |
JPH11121932A (ja) * | 1997-10-17 | 1999-04-30 | Ibiden Co Ltd | 多層配線板及び多層プリント配線板 |
US6064114A (en) | 1997-12-01 | 2000-05-16 | Motorola, Inc. | Semiconductor device having a sub-chip-scale package structure and method for forming same |
JP3381601B2 (ja) * | 1998-01-26 | 2003-03-04 | 松下電器産業株式会社 | バンプ付電子部品の実装方法 |
JP3514361B2 (ja) | 1998-02-27 | 2004-03-31 | Tdk株式会社 | チップ素子及びチップ素子の製造方法 |
JP3420703B2 (ja) * | 1998-07-16 | 2003-06-30 | 株式会社東芝 | 半導体装置の製造方法 |
US6400018B2 (en) | 1998-08-27 | 2002-06-04 | 3M Innovative Properties Company | Via plug adapter |
US6903451B1 (en) * | 1998-08-28 | 2005-06-07 | Samsung Electronics Co., Ltd. | Chip scale packages manufactured at wafer level |
KR20000032827A (ko) * | 1998-11-18 | 2000-06-15 | 구자홍 | 다층 회로기판의 접점부 형성방법 |
JP3577419B2 (ja) * | 1998-12-17 | 2004-10-13 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
JP2000223653A (ja) * | 1999-02-02 | 2000-08-11 | Rohm Co Ltd | チップ・オン・チップ構造の半導体装置およびそれに用いる半導体チップ |
US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
JP3128548B2 (ja) * | 1999-03-11 | 2001-01-29 | 沖電気工業株式会社 | 半導体装置および半導体装置の製造方法 |
JP3446825B2 (ja) * | 1999-04-06 | 2003-09-16 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
JP2001144197A (ja) | 1999-11-11 | 2001-05-25 | Fujitsu Ltd | 半導体装置、半導体装置の製造方法及び試験方法 |
US6513236B2 (en) * | 2000-02-18 | 2003-02-04 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing bump-component mounted body and device for manufacturing the same |
TW494517B (en) * | 2000-03-17 | 2002-07-11 | Matsushita Electric Ind Co Ltd | Method and apparatus for evaluating insulation film |
JP2002057252A (ja) * | 2000-08-07 | 2002-02-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002118199A (ja) * | 2000-10-10 | 2002-04-19 | Mitsubishi Electric Corp | 半導体装置 |
JP4557461B2 (ja) * | 2001-06-26 | 2010-10-06 | 京セラ株式会社 | 配線基板 |
DE10231385B4 (de) * | 2001-07-10 | 2007-02-22 | Samsung Electronics Co., Ltd., Suwon | Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung |
KR100415687B1 (ko) * | 2001-07-19 | 2004-01-24 | 에쓰에쓰아이 주식회사 | 반도체 칩 스케일 패키지 및 그 제조방법 |
US7759803B2 (en) * | 2001-07-25 | 2010-07-20 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20040099716A1 (en) * | 2002-11-27 | 2004-05-27 | Motorola Inc. | Solder joint reliability by changing solder pad surface from flat to convex shape |
JP2004200394A (ja) * | 2002-12-18 | 2004-07-15 | Nitto Denko Corp | 半導体装置の製造方法 |
BRPI0411160A (pt) | 2003-05-12 | 2006-07-11 | Affymax Inc | novos compostos modificados com poli(glicol etilênico) e usos dos mesmos |
EP1628686A2 (en) | 2003-05-12 | 2006-03-01 | Affymax, Inc. | Spacer moiety for poly (ethylene glycol)-modified peptides |
JP3678239B2 (ja) * | 2003-06-30 | 2005-08-03 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US7303941B1 (en) | 2004-03-12 | 2007-12-04 | Cisco Technology, Inc. | Methods and apparatus for providing a power signal to an area array package |
US7446399B1 (en) | 2004-08-04 | 2008-11-04 | Altera Corporation | Pad structures to improve board-level reliability of solder-on-pad BGA structures |
TW200717743A (en) * | 2005-10-03 | 2007-05-01 | Rohm Co Ltd | Semiconductor device |
US20080088035A1 (en) * | 2006-10-17 | 2008-04-17 | Hon Hai Precision Industry Co., Ltd. | Circuit board assembly |
JP4980709B2 (ja) * | 2006-12-25 | 2012-07-18 | ローム株式会社 | 半導体装置 |
EP2114427B1 (en) | 2007-01-30 | 2014-06-25 | New York University | Peptides for treatment of conditions associated with nitric oxide |
JP2008207543A (ja) * | 2007-01-31 | 2008-09-11 | Canon Inc | インクジェット記録へッドおよびその製造方法 |
JP4679553B2 (ja) * | 2007-07-23 | 2011-04-27 | イビデン株式会社 | 半導体チップ |
US20120074558A1 (en) * | 2010-09-29 | 2012-03-29 | Mao Bang Electronic Co., Ltd. | Circuit Board Packaged with Die through Surface Mount Technology |
US9484259B2 (en) | 2011-09-21 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
US9082832B2 (en) | 2011-09-21 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming protection and support structure for conductive interconnect structure |
JP6326723B2 (ja) * | 2012-08-24 | 2018-05-23 | Tdk株式会社 | 端子構造及び半導体素子 |
JP6015240B2 (ja) | 2012-08-24 | 2016-10-26 | Tdk株式会社 | 端子構造及び半導体素子 |
JP6155571B2 (ja) | 2012-08-24 | 2017-07-05 | Tdk株式会社 | 端子構造、並びにこれを備える半導体素子及びモジュール基板 |
US9086433B2 (en) * | 2012-12-19 | 2015-07-21 | International Business Machines Corporation | Rigid probe with compliant characteristics |
US20140252073A1 (en) * | 2013-03-05 | 2014-09-11 | Summit Imaging, Inc. | Ball grid array mounting system and method |
US11103593B2 (en) | 2013-10-15 | 2021-08-31 | Seagen Inc. | Pegylated drug-linkers for improved ligand-drug conjugate pharmacokinetics |
TWI569368B (zh) | 2015-03-06 | 2017-02-01 | 恆勁科技股份有限公司 | 封裝基板、包含該封裝基板的封裝結構及其製作方法 |
US9484227B1 (en) * | 2015-06-22 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dicing in wafer level package |
US11793880B2 (en) | 2015-12-04 | 2023-10-24 | Seagen Inc. | Conjugates of quaternized tubulysin compounds |
AU2016363013B2 (en) | 2015-12-04 | 2022-03-10 | Seagen Inc. | Conjugates of quaternized tubulysin compounds |
AU2017237186A1 (en) | 2016-03-25 | 2018-11-01 | Seagen Inc. | Process for the preparation of PEGylated drug-linkers and intermediates thereof |
US10120971B2 (en) * | 2016-08-30 | 2018-11-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and layout method thereof |
JP7244987B2 (ja) | 2016-12-14 | 2023-03-23 | シージェン インコーポレイテッド | 多剤抗体薬物コンジュゲート |
US11730822B2 (en) | 2017-03-24 | 2023-08-22 | Seagen Inc. | Process for the preparation of glucuronide drug-linkers and intermediates thereof |
TW202015740A (zh) | 2018-06-07 | 2020-05-01 | 美商西雅圖遺傳學公司 | 喜樹鹼結合物 |
US11081369B2 (en) * | 2019-02-25 | 2021-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and manufacturing method thereof |
CN114929284A (zh) | 2019-10-04 | 2022-08-19 | 西根公司 | 喜树碱肽缀合物 |
US11289431B2 (en) * | 2019-12-27 | 2022-03-29 | Intel Corporation | Electrostatic discharge protection in integrated circuits using materials with optically controlled electrical conductivity |
IL297167A (en) | 2020-04-10 | 2022-12-01 | Seagen Inc | Charging variant connectors |
BR112023014128A2 (pt) | 2021-01-15 | 2023-10-31 | Seagen Inc | Conjugados de anticorpo-fármaco imunomodulatórios |
US20220246508A1 (en) * | 2021-01-29 | 2022-08-04 | Mediatek Inc. | Ball pad design for semiconductor packages |
WO2022170002A1 (en) | 2021-02-03 | 2022-08-11 | Seagen Inc. | Immunostimulatory compounds and conjugates |
CA3221398A1 (en) | 2021-05-28 | 2022-12-01 | Seagen Inc. | Anthracycline antibody conjugates |
WO2023083919A1 (en) | 2021-11-09 | 2023-05-19 | Tubulis Gmbh | Conjugates comprising a phosphorus (v) and a camptothecin moiety |
WO2023083900A1 (en) | 2021-11-09 | 2023-05-19 | Tubulis Gmbh | Conjugates comprising a phosphorus (v) and a drug moiety |
WO2023178289A2 (en) | 2022-03-17 | 2023-09-21 | Seagen Inc. | Camptothecin conjugates |
WO2023215740A1 (en) | 2022-05-06 | 2023-11-09 | Seagen Inc. | Immunomodulatory antibody-drug conjugates |
WO2024030577A1 (en) | 2022-08-03 | 2024-02-08 | Seagen Inc. | Immunostimulatory anti-pd-l1-drug conjugates |
EP4321522A1 (en) | 2022-08-12 | 2024-02-14 | Seagen Inc. | Cytotoxic compounds and conjugates thereof |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5518069A (en) * | 1978-07-26 | 1980-02-07 | Citizen Watch Co Ltd | Protective construction of semiconductor device |
JPS62144346A (ja) * | 1985-12-19 | 1987-06-27 | Matsushita Electric Ind Co Ltd | 半導体集積回路素子 |
JPH0744345B2 (ja) * | 1989-10-20 | 1995-05-15 | 株式会社富士通ゼネラル | 多層配線基板 |
JP2570468B2 (ja) * | 1990-06-01 | 1997-01-08 | 日本電気株式会社 | Lsiモジュールの製造方法 |
JPH04118958A (ja) * | 1990-09-10 | 1992-04-20 | Toshiba Corp | 表面実装用多層型配線基板 |
US5289346A (en) * | 1991-02-26 | 1994-02-22 | Microelectronics And Computer Technology Corporation | Peripheral to area adapter with protective bumper for an integrated circuit chip |
JPH0536889A (ja) * | 1991-07-26 | 1993-02-12 | Hitachi Ltd | 半導体装置 |
KR950012658B1 (ko) * | 1992-07-24 | 1995-10-19 | 삼성전자주식회사 | 반도체 칩 실장방법 및 기판 구조체 |
JPH06120296A (ja) * | 1992-10-07 | 1994-04-28 | Hitachi Ltd | 半導体集積回路装置 |
US5510758A (en) * | 1993-04-07 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps |
JPH07106503A (ja) * | 1993-10-08 | 1995-04-21 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージおよび半導体装置 |
JP2833996B2 (ja) * | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | フレキシブルフィルム及びこれを有する半導体装置 |
JPH08236586A (ja) * | 1994-12-29 | 1996-09-13 | Nitto Denko Corp | 半導体装置及びその製造方法 |
-
1995
- 1995-04-27 JP JP7103812A patent/JP2763020B2/ja not_active Expired - Fee Related
-
1996
- 1996-04-24 US US08/637,281 patent/US5757078A/en not_active Expired - Lifetime
- 1996-04-27 KR KR1019960014141A patent/KR100248682B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPH08306743A (ja) | 1996-11-22 |
JP2763020B2 (ja) | 1998-06-11 |
KR100248682B1 (ko) | 2000-03-15 |
US5757078A (en) | 1998-05-26 |
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