KR960042902A - 솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지 - Google Patents

솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지 Download PDF

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KR960042902A
KR960042902A KR1019950014293A KR19950014293A KR960042902A KR 960042902 A KR960042902 A KR 960042902A KR 1019950014293 A KR1019950014293 A KR 1019950014293A KR 19950014293 A KR19950014293 A KR 19950014293A KR 960042902 A KR960042902 A KR 960042902A
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pattern layer
solder ball
pad
circuit board
mounting groove
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KR1019950014293A
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KR0157284B1 (ko
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오상언
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김광호
삼성전자 주식회사
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Priority to JP7197412A priority patent/JP2768650B2/ja
Priority to US08/512,013 priority patent/US5636104A/en
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
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    • H05K2203/04—Soldering or other types of metallurgic bonding
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Abstract

본 발명은 다수의 입출력 핀을 갖는 반도체 소자를 패키지하는 볼 그리드 어레이(BGA) 패키지에 관한 것으로서, 복수의 전도성 패턴 층으로 이루어진 인쇄 회로기판(PCB)의 가장 바깥쪽 패턴 층의 솔더 볼이 부착될 부분에 구멍을 뚫고 이 패턴 층 바로 다음 층에는 상기 구멍에 해당하는 위치에 구리 패드를 형성한다. 바깥쪽 패턴 층의 구멍 주위에는 구리 패드를 도포함으로써, 외부 패드(22)와 내부 패드(23)로 구성된 오목 홈 형태의 솔더 볼 부착 패드를 형성한다. 여기서, 홈의 깊이는 외부 패드가 형성된 패턴 층과 내부 패드가 형성된 패턴층의 층간 두께와 같으며, 홈의 크기는 사용하는 솔더 볼의 크기에 따라 조정된다. 이러한 구조를 갖는 솔더 볼 패드에솔더 볼을 올려놓고 리플로 솔더 공정을 하면, 솔더 볼이 내부 패드와 외부 패드에 모두 녹아붙기 때문에 솔더 볼과 기판과의 결합력이 강화되고, 솔더볼에서 발생하기 쉬운 크랙을 방지하며 솔더 볼의 전체 높이를 낮출 수 있다는 장점이 있다.

Description

솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 구조를 갖는 인쇄 회로 기판을 사용한 볼 그리드 어레이 패키지 부분 단면도, 제5도는 본 발명에 따른 구조을 갖는 인쇄 회로 기판의 구조 설명도, 제6A도 및 제6B도는 본 발명에 따른 구조를 갖는 인쇄 회로 기판에 솔더 볼을 놓로 리플로 솔더 공정을 통해 솔더 볼 장착 홈에 부착시킨 부분 확대도, 제7도는 본 발명에 따른 인쇄 회로 기판에 솔더 볼 대신에 구리나 합금으로 이루어진 금속 칼럼을 사용한 볼 그리드 어레이 패키지의 부분 단면도.

Claims (6)

  1. 반도체 칩과, 상기 반도체 칩이 탑재되며 소정의 전도성 패턴이 형성된 제1패턴 층과 제2패턴 층을 포함하는 복수의 패턴 층으로 이루어진 회로 기판과, 상기 반도체 칩을 보호하기 위한 몰딩 수지와, 상기 소정의 전도성 패턴을 통해 상기 반도체 칩과 전기적으로 연결되며 상기 회로 기판 밑면에 부착되는 복수의 솔더 볼을 구비하는 볼 그리드 어레이 반도체 패키지에 있어서, 상기 복수의 솔더 볼이 부착되는 상기 회로 기판의 상기 제1패턴 층에는 제1전도성 패드가 형성되어 있고 상기 제2패턴 층에는 제2전도성 패드가 형성되어 있어서 상기 제1패턴 층과 제2패턴 층의 층간 간격만큼의 깊이를 갖는 솔더 볼장착 홈이 구비되어 있는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지.
  2. 제1항에 있어서, 상기 솔더 볼 장착 홈의 너비는 상기 솔더 볼의 지름보다 작거나 같은 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지.
  3. 제1항 또는 제2항에 있어서, 상기 솔더 볼은 구리나 합금으로 이루어진 금속 칼럼인 것을 특징으로 하는 볼그리드 어레이 반도체 패키지.
  4. 제1항 또는 제2항에 있어서, 상기 솔더 볼 장착 홈에 장착된 상기 복수의 솔더 볼 각각은 상기 제1전도성 패드와 제2전도성 패드에 용융 접합되어서 버섯 모양을 갖는 것을 특징으로 하는 볼 그리드 어레이 반도체 패키지.
  5. 소정의 전도성 패턴이 형성되어 있는 제1패턴 층과 제2패턴 층을 포함하는 복수의 패턴 층과 상기 복수의 패턴 층 사이에 삽입되는 유전 물질을 구비하는 회로 기판에 있어서, 상기 제1패턴 층에는 제1전기 전도성 패드가 패턴 형성되어 있고 상기 제2패턴 층에는 제2전기 전도성 패드가 패턴 형성되어 있으며, 상기 제1전도성 패드와 제2전도성 패드는 상기 제1패턴 층과 제2패턴 층 사이의 유전 물질의 두께 만큼의 깊이를 가지는 솔더 볼 장착 홈을 구성하는 것을 특징으로 하는 회로 기판.
  6. 제5항에 있어서, 상기 솔더 볼 장착 홈의 너비는 상기 장착 홈에 장착되는 솔더 볼의 지름보다 작거나 같은 것을 특징으로 하는 회로 기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950014293A 1995-05-31 1995-05-31 솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지 KR0157284B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950014293A KR0157284B1 (ko) 1995-05-31 1995-05-31 솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지
JP7197412A JP2768650B2 (ja) 1995-05-31 1995-08-02 ソルダーボールの装着溝を有する印刷回路基板とこれを使用したボールグリッドアレイパッケージ
US08/512,013 US5636104A (en) 1995-05-31 1995-08-07 Printed circuit board having solder ball mounting groove pads and a ball grid array package using such a board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950014293A KR0157284B1 (ko) 1995-05-31 1995-05-31 솔더 볼 장착홈을 갖는 인쇄 회로 기판과 이를 사용한 볼 그리드 어레이 패키지

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KR960042902A true KR960042902A (ko) 1996-12-21
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100450246B1 (ko) * 1997-06-30 2005-05-24 삼성전자주식회사 솔더 볼 부착 장치
KR100544969B1 (ko) * 1997-03-13 2006-01-24 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
KR100702967B1 (ko) * 2000-12-01 2007-04-03 삼성전자주식회사 솔더 볼 부착 홈이 형성된 리드 프레임을 포함하는 반도체패키지 및 그를 이용한 적층 패키지

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861290B1 (en) * 1995-12-19 2005-03-01 Micron Technology, Inc. Flip-chip adaptor package for bare die
US5719440A (en) 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
US6635514B1 (en) * 1996-12-12 2003-10-21 Tessera, Inc. Compliant package with conductive elastomeric posts
US6417029B1 (en) * 1996-12-12 2002-07-09 Tessera, Inc. Compliant package with conductive elastomeric posts
CN1971899B (zh) * 1997-10-17 2010-05-12 揖斐电株式会社 封装基板
US6116921A (en) * 1998-02-16 2000-09-12 The Whitaker Corporation Electrical connector having recessed solderball foot
JPH11274813A (ja) * 1998-03-24 1999-10-08 Ngk Spark Plug Co Ltd 誘電体フィルタ及びその製造方法
JPH11297889A (ja) * 1998-04-16 1999-10-29 Sony Corp 半導体パッケージおよび実装基板、ならびにこれらを用いた実装方法
USRE43112E1 (en) 1998-05-04 2012-01-17 Round Rock Research, Llc Stackable ball grid array package
DE19839760A1 (de) * 1998-09-01 2000-03-02 Bosch Gmbh Robert Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung
US6352437B1 (en) 1999-10-20 2002-03-05 John O. Tate Solder ball terminal
SG106050A1 (en) * 2000-03-13 2004-09-30 Megic Corp Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby
US6333563B1 (en) 2000-06-06 2001-12-25 International Business Machines Corporation Electrical interconnection package and method thereof
KR100374629B1 (ko) * 2000-12-19 2003-03-04 페어차일드코리아반도체 주식회사 얇고 작은 크기의 전력용 반도체 패키지
CN1498076A (zh) * 2001-03-20 2004-05-19 �ȿ˻�ѧ�ɷ����޹�˾ 植物药物熔合组合物
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
KR100481216B1 (ko) * 2002-06-07 2005-04-08 엘지전자 주식회사 볼 그리드 어레이 패키지 및 그의 제조 방법
KR100546832B1 (ko) 2003-08-21 2006-01-26 삼성전자주식회사 임베디드 ｐｃｂ 기판을 사용한 듀플렉서 및 그 제조 방법
TWI233677B (en) * 2003-10-28 2005-06-01 Advanced Semiconductor Eng Ball grid array package and method thereof
JP4828997B2 (ja) * 2006-04-24 2011-11-30 ルネサスエレクトロニクス株式会社 半導体パッケージおよびその実装方法、ならびにその半導体パッケージに使用する絶縁配線基板およびその製造方法
WO2010005592A2 (en) 2008-07-09 2010-01-14 Tessera, Inc. Microelectronic interconnect element with decreased conductor spacing
US8259415B2 (en) * 2009-06-22 2012-09-04 Seagate Technology Llc Slider bond pad with a recessed channel
US8671560B2 (en) 2010-03-30 2014-03-18 Research Triangle Institute In system reflow of low temperature eutectic bond balls
US9814190B1 (en) 2013-02-01 2017-11-14 Hunter Industries, Inc. Irrigation controller with robust ground path
CN104425287A (zh) * 2013-08-19 2015-03-18 讯芯电子科技（中山）有限公司 封装结构及制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60241228A (ja) * 1984-05-16 1985-11-30 Hitachi Comput Eng Corp Ltd 半導体チツプ
JPS62266857A (ja) * 1986-05-15 1987-11-19 Oki Electric Ind Co Ltd 半導体装置
JPS63239873A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd マルチチツプモジユ−ル
US4940181A (en) * 1989-04-06 1990-07-10 Motorola, Inc. Pad grid array for receiving a solder bumped chip carrier
DE68927931T2 (de) * 1989-07-26 1997-09-18 Ibm Verfahren zur Herstellung einer Packungsstruktur für einen integrierten Schaltungschip
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JPH0472792A (ja) * 1990-07-13 1992-03-06 Nec Ibaraki Ltd チップキャリアの実装構造
US5128746A (en) * 1990-09-27 1992-07-07 Motorola, Inc. Adhesive and encapsulant material with fluxing properties
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
JPH08279571A (ja) * 1995-04-10 1996-10-22 Shinko Electric Ind Co Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100544969B1 (ko) * 1997-03-13 2006-01-24 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
US7339118B1 (en) 1997-03-13 2008-03-04 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US7612295B2 (en) 1997-03-13 2009-11-03 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
KR100450246B1 (ko) * 1997-06-30 2005-05-24 삼성전자주식회사 솔더 볼 부착 장치
KR100702967B1 (ko) * 2000-12-01 2007-04-03 삼성전자주식회사 솔더 볼 부착 홈이 형성된 리드 프레임을 포함하는 반도체패키지 및 그를 이용한 적층 패키지

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JP2768650B2 (ja) 1998-06-25
JPH08330473A (ja) 1996-12-13
KR0157284B1 (ko) 1999-02-18
US5636104A (en) 1997-06-03

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