KR950034482A - 반도체 소자의 다층금속 배선의 형성방법 - Google Patents

반도체 소자의 다층금속 배선의 형성방법 Download PDF

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KR950034482A
KR950034482A KR1019940010217A KR19940010217A KR950034482A KR 950034482 A KR950034482 A KR 950034482A KR 1019940010217 A KR1019940010217 A KR 1019940010217A KR 19940010217 A KR19940010217 A KR 19940010217A KR 950034482 A KR950034482 A KR 950034482A
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metal layer
metal
layer
forming
kpa
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KR1019940010217A
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KR0124644B1 (ko
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박내학
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문정환
금성일렉트론 주식회사
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Priority to KR1019940010217A priority Critical patent/KR0124644B1/ko
Priority to JP7128838A priority patent/JPH07307385A/ja
Publication of KR950034482A publication Critical patent/KR950034482A/ko
Priority to US08/688,676 priority patent/US5663102A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

본 발명은 반도체 소자의 다층금속 배선의 형성방법에 관한 것으로, 콘택오픈의 현상을 방지하고 반도체 소자의 스피드를 향상시키는 효과가 있다.
이와 같은 본 발명은 반도체 기판상에 제1유전체층을 형성하고 제1금속층을 페턴닝하는 제1공정과, 전면에 제2유전체층을 형성하고 상기 제1금속층과 형성될 제2금속층의 접촉을 위해 배선용 콘택홀을 형성하는 제2공정과, 전면에 제2금속층과 제3금속층을 차례로 형성하고 상기 제2유전체층이 노출될 때까지 상기 제2, 제3금속층을 제거하여 다층금속 패턴을 형성하는 제3공정을 포함하여 이루어지는 반도체 소자의 다층금속 배선이 형성방법이다.

Description

반도체 소자의 다층금속 배선의 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 반도체 소자의 제1실시예를 나타낸 다층금속 배선의 형성공정 단면도, 제3도는 본 발명의 반도체 소자의 제2실시예를 나타낸 다층금속 배선의 형성공정 단면도, 제4도는 본 발명의 반도체 소자의 제3실시예를 나타낸 다층금속 배선의 형성공정 단면도.

Claims (8)

  1. 반도체 기판상에 제1유전체층을 형성하고 제1금속층을 패턴닝하는 제1공정과, 전면에 제2유전체층을 형성하고 상기 제1금속층과 형성될 제2금속층의 접촉을 위해 배선용 콘택홀을 형성하는 제2공정과, 전면에 제2금속층과 제3금속층을 차례로 형성하고 상기 제2유전체층이 노출될 때까지 상기 제2, 제3금속층을 제거하여 다층금속 패턴을 형성하는 제3공정을 포함하여 이루어짐을 특징으로 하는 반도체 소자의 다층금속 배선의 형성방법.
  2. 제1항에 있어서, 상기 제2금속층은 알루미늄을 스퍼터닝 공정으로, 제3금속층은 텅스텐을 씨이브이디 공정으로 차례로 증착하여 형성함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
  3. 제1항에 있어서, 상기 제2금속층은 텅스텐을 씨이브이디 공정으로, 제3금속층은 알루미늄을 스퍼터닝 공정으로 차례로 증착하여 형성함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
  4. 제1항에 있어서, 상기 제2공정이 제2금속층과 제3금속층을 차례로 적층하여 제3금속층위에 더 증착함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
  5. 제4항에 있어서, 제2금속, 제3금속, 제2금속층으로 텡스텐을 씨이브이디 공정으로 알루미늄을 스퍼터닝 공정으로, 텡스텐을 씨이브이디 공정으로 차례로 증착하여 형성함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
  6. 제1항 또는 제2항에 있어서, 상기 제2금속과 제3금속층의 두께는 각각 500Å~2000Å, 500Å~5000Å으로 형성함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
  7. 제1항 또는 제3항에 있어서, 상기 제2금속과 제3금속층의 두께는 각각 500Å~2000Å, 500Å~5000Å으로 형성함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
  8. 제4항 또는 제5항에 있어서, 상기 제2금속층, 제3금속층의 적층 두께는 각각 500Å~2000Å, 500Å~2000Å, 500Å~2000Å으로 형성함을 특징으로 하는 반도체 소자의 다층 금속 배선의 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940010217A 1994-05-10 1994-05-10 반도체소자의 다층금속배선의 형성방법 KR0124644B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019940010217A KR0124644B1 (ko) 1994-05-10 1994-05-10 반도체소자의 다층금속배선의 형성방법
JP7128838A JPH07307385A (ja) 1994-05-10 1995-05-01 半導体素子の多層金属配線の形成方法
US08/688,676 US5663102A (en) 1994-05-10 1996-07-29 Method for forming multi-layered metal wiring semiconductor element using cmp or etch back

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940010217A KR0124644B1 (ko) 1994-05-10 1994-05-10 반도체소자의 다층금속배선의 형성방법

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KR950034482A true KR950034482A (ko) 1995-12-28
KR0124644B1 KR0124644B1 (ko) 1997-12-11

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Publication number Publication date
US5663102A (en) 1997-09-02
KR0124644B1 (ko) 1997-12-11
JPH07307385A (ja) 1995-11-21

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