KR970053510A - 다층배선 형성방법 - Google Patents

다층배선 형성방법 Download PDF

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Publication number
KR970053510A
KR970053510A KR1019950046369A KR19950046369A KR970053510A KR 970053510 A KR970053510 A KR 970053510A KR 1019950046369 A KR1019950046369 A KR 1019950046369A KR 19950046369 A KR19950046369 A KR 19950046369A KR 970053510 A KR970053510 A KR 970053510A
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South Korea
Prior art keywords
metal
layer
buffer layer
wiring
multilayer wiring
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KR1019950046369A
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English (en)
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KR100192553B1 (ko
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공유상
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문정환
Lg 반도체주식회사
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Priority to KR1019950046369A priority Critical patent/KR100192553B1/ko
Publication of KR970053510A publication Critical patent/KR970053510A/ko
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Publication of KR100192553B1 publication Critical patent/KR100192553B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다층배선 형성방법에 관한 것으로, 다층배선 공정시 차기(次期) 금속배선의 재작업이 가능하도록 하는데 적당한 다층배선 형성방법을 제공하기 위한 것이다. 이를 위한 본 발명의 다층배선 형성방법은 기판상의 산화막을 선택적으로 제거한 후, 전면에 베리어 메탈층, 제1금속층, 버퍼층을 차례로 형성하는 공정, 상기 버퍼층상에 감광막을 도포하여 불필요한 버퍼층, 제1금속층, 베리어 메탈층을 선택적으로 제거하는 공정, 상기 버퍼층 상부에 절연막을 중착하고 이를 선택적으로 제거하여 상기 버퍼층과 연결되도록 비아 콘택홀을 형성하는 공정, 상기 비아 콘택홀을 포함한 절연막상에 제2금속을 중착하여 제2금속배선을 포함하여 이루어짐을 특징으로 한다.

Description

다층배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (a) ~ (b)는 본 발명의 다층배선 형성방법을 나타낸 공정단면도.

Claims (4)

  1. 기판상의 산화막을 선택적으로 제거한 후, 전면에 베리어 메탈층, 제1금속층, 버퍼층을 차례로 형성하는 공정, 상기 버퍼층상에 감광막을 도포하여 불필요한 버퍼층, 제1금속층, 베리어 메탈층을 선택적으로 제거하는 공정, 상기 버퍼층 상부에 절연막을 증착하고 이를 선택적으로 제거하여 상기 버퍼층과 연결되도록 비아 콘택홀을 형성하는 공정, 상기 비아 콘택홀을 포함한 절연막상에 제2금속을 증착하여 제2금속배선을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 다층배선 형성방법.
  2. 제1항에 있어서, 상기 제2금속배선을 재작업할 경우, 상기 제2금속배선과 상기 버퍼층의 식각선택비가 서로 다른 식각용액을 통해 상기 제2금속배선을 제거하는 공정을 추가로 포함하여 이루어짐을 특징으로 하는 다층배선 형성방법.
  3. 제1항에 있어서, 상기 버퍼층은 티타늄/텅스텐층이며 그 두께는 500±200A 정도이고, 그 비율은 티타늄이 10% 텅스텐이 90%로 함을 특징으로 하는 다층배선 형성방법.
  4. 제2항에 있어서, 상기 식각용액은 질산, 인산, 초산, 그리고 물의 비율이 1:15:3:1의 비율을 갖는 용액임을 특징으로 하는 다층배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950046369A 1995-12-04 1995-12-04 다층배선 형성방법 KR100192553B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950046369A KR100192553B1 (ko) 1995-12-04 1995-12-04 다층배선 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950046369A KR100192553B1 (ko) 1995-12-04 1995-12-04 다층배선 형성방법

Publications (2)

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KR970053510A true KR970053510A (ko) 1997-07-31
KR100192553B1 KR100192553B1 (ko) 1999-06-15

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