KR920020619A - 텅스텐플러그의 형성방법 - Google Patents

텅스텐플러그의 형성방법 Download PDF

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Publication number
KR920020619A
KR920020619A KR1019920005548A KR920005548A KR920020619A KR 920020619 A KR920020619 A KR 920020619A KR 1019920005548 A KR1019920005548 A KR 1019920005548A KR 920005548 A KR920005548 A KR 920005548A KR 920020619 A KR920020619 A KR 920020619A
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KR
South Korea
Prior art keywords
tungsten
forming
layer
opening
smoothed
Prior art date
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KR1019920005548A
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English (en)
Inventor
마사가즈 무로야마
쥰이찌 사또
Original Assignee
오가 노리오
소니 가부시기가이샤
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Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920020619A publication Critical patent/KR920020619A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

텅스텐플러그의 형성방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 텅스텐플러그의 형성방법의 일예에 있어서의 콘택트홀의 형성공정까지의 공정단면도,
제2도는 본원 발명의 텅스텐플러그의 형성방법의 일예에 있어서의 선택텅스텐 CVD공정까지의 공정단면도,
제3도는 본원 발명의 텅스텐플러그의 형성방법의 일예에 있어서의 평활화처리공정까지의 공정단면도,
제4도는 본원 발명의 텅스텐플러그의 형성방법의 일예에 있어서의 퇴적물의 제거공정까지의 공정단면도,
제5도는 본원 발명의 텅스텐플러그의 형성방법의 일예에 있어서의 금속배선층의 형성공정까지의 공정단면도.

Claims (3)

  1. 층간절연막의 개구부에 텅스텐플러그를 형성하는 방법에 있어서, 상기 개구부내에 선택텅스텐법에 의해 텅스텐층을 얇게 형성한후, 그 텅스텐층의 표면을 평활처리하고, 그 평활화처리된 텅스텐층상에 다시 금속배선층을 적층시키는 것을 특징으로 하는 텅스텐플러그의 형성방법.
  2. 층간절연막의 개구부에 텅스텐플러그를 형성하는 방법에 있어서, 상기 개구부내 및 층간절연막상에 블랭킷텅스텐법에 의해 텅스텐층을 형성한 후, 그 텅스텐층의 표면을 평활화처리하고, 그 평활처리된 텅스텐층을 에치백하는 것을 특징으로 하는 텅스텐플러그의 형성방법.
  3. 층간절연막의 개구부에 텅스텐플러그를 형성하는 방법에 있어서, 상기 개구부내에 선택텅스텐법에 의해 텅스텐층을 얇게 형성한 후, 그 텅스텐층의 표면을 평활화처리하고, 상기 층간절연막 및 상기 개구부내의 평활화된 텅스텐층상에 블랭킷텅스텐법에 의해 텅스텐층을 적층시키고, 그 텅스텐층을 에치백하는 것을 특징으로 하는 텅스텐플러그의 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920005548A 1991-04-05 1992-04-03 텅스텐플러그의 형성방법 KR920020619A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-099771 1991-04-05
JP3099771A JPH04307933A (ja) 1991-04-05 1991-04-05 タングステンプラグの形成方法

Publications (1)

Publication Number Publication Date
KR920020619A true KR920020619A (ko) 1992-11-21

Family

ID=14256234

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005548A KR920020619A (ko) 1991-04-05 1992-04-03 텅스텐플러그의 형성방법

Country Status (3)

Country Link
US (1) US5260232A (ko)
JP (1) JPH04307933A (ko)
KR (1) KR920020619A (ko)

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US6355553B1 (en) * 1992-07-21 2002-03-12 Sony Corporation Method of forming a metal plug in a contact hole
US5783471A (en) * 1992-10-30 1998-07-21 Catalyst Semiconductor, Inc. Structure and method for improved memory arrays and improved electrical contacts in semiconductor devices
US5633201A (en) * 1992-11-30 1997-05-27 Hyundai Electronics Industries, Co., Ltd. Method for forming tungsten plugs in contact holes of a semiconductor device
US5776827A (en) * 1993-08-27 1998-07-07 Yamaha Corporation Wiring-forming method
JP3382357B2 (ja) * 1993-08-27 2003-03-04 ヤマハ株式会社 配線形成方法
JPH07130852A (ja) * 1993-11-02 1995-05-19 Sony Corp 金属配線材料の形成方法
US5599739A (en) * 1994-12-30 1997-02-04 Lucent Technologies Inc. Barrier layer treatments for tungsten plug
US5489552A (en) * 1994-12-30 1996-02-06 At&T Corp. Multiple layer tungsten deposition process
US6979632B1 (en) * 1995-07-13 2005-12-27 Semiconductor Energy Laboratory Co., Ltd. Fabrication method for thin-film semiconductor
GB2307341B (en) * 1995-11-15 2000-06-14 Hyundai Electronics Ind Method of forming a tungsten plug of a semiconductor device
US6462394B1 (en) 1995-12-26 2002-10-08 Micron Technology, Inc. Device configured to avoid threshold voltage shift in a dielectric film
US7067442B1 (en) * 1995-12-26 2006-06-27 Micron Technology, Inc. Method to avoid threshold voltage shift in thicker dielectric films
US5693561A (en) * 1996-05-14 1997-12-02 Lucent Technologies Inc. Method of integrated circuit fabrication including a step of depositing tungsten
KR100193897B1 (ko) * 1996-06-28 1999-06-15 김영환 반도체 소자의 플러그 형성 방법
KR100214852B1 (ko) * 1996-11-02 1999-08-02 김영환 반도체 디바이스의 금속 배선 형성 방법
KR100431710B1 (ko) * 1996-12-30 2004-08-06 주식회사 하이닉스반도체 반도체장치의금속배선형성방법
US6025271A (en) 1997-12-08 2000-02-15 Micron Technology, Inc. Method of removing surface defects or other recesses during the formation of a semiconductor device
KR100295639B1 (ko) * 1998-01-14 2001-08-07 김영환 플러그형성방법
TW436366B (en) * 1998-08-21 2001-05-28 United Microelectronics Corp Method of fabricating a plug
KR100375230B1 (ko) * 2000-12-20 2003-03-08 삼성전자주식회사 매끄러운 텅스텐 표면을 갖는 반도체 장치의 배선 제조방법
US6828678B1 (en) * 2002-03-29 2004-12-07 Silicon Magnetic Systems Semiconductor topography with a fill material arranged within a plurality of valleys associated with the surface roughness of the metal layer
KR100538097B1 (ko) * 2003-04-24 2005-12-21 삼성전자주식회사 금속막 제조 방법 및 이를 이용한 반도체 장치의 제조 방법
US8778797B2 (en) * 2010-09-27 2014-07-15 Novellus Systems, Inc. Systems and methods for selective tungsten deposition in vias

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Also Published As

Publication number Publication date
US5260232A (en) 1993-11-09
JPH04307933A (ja) 1992-10-30

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