KR960005850A - 반도체장치의 층간절연막 형성방법 - Google Patents

반도체장치의 층간절연막 형성방법 Download PDF

Info

Publication number
KR960005850A
KR960005850A KR1019940017850A KR19940017850A KR960005850A KR 960005850 A KR960005850 A KR 960005850A KR 1019940017850 A KR1019940017850 A KR 1019940017850A KR 19940017850 A KR19940017850 A KR 19940017850A KR 960005850 A KR960005850 A KR 960005850A
Authority
KR
South Korea
Prior art keywords
insulating film
forming
wiring
semiconductor device
interlayer insulating
Prior art date
Application number
KR1019940017850A
Other languages
English (en)
Other versions
KR0144950B1 (ko
Inventor
오희선
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940017850A priority Critical patent/KR0144950B1/ko
Publication of KR960005850A publication Critical patent/KR960005850A/ko
Application granted granted Critical
Publication of KR0144950B1 publication Critical patent/KR0144950B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체장치의 층간절연막 형성방법이 개시되어 있다. 배선이 형성되어 있는 반도체기판 상에 절연막을 침적하고, 상기 절연막을 이방성 식각하여 배선의 측벽에 스페이서를 형성한다. 금속배선의 라인 스페이스에 보이드가 발생하지 않아 디자인 룰을 축소할 수 있다.

Description

반도체장치의 층간절연막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2F는 본 발명에 의한 층간절연막 형성방법을 설명하기 위한 단면도들이다.

Claims (3)

  1. 배선이 형성되어 있는 반도체기판 상에 절연막을 형성하는 단계; 및 상기 절연막을 이방성 식각하여 상기 배선의 측벽에 스페이서를 형성하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 층간절연막 형성방법.
  2. 제1항에 있어서, 상기 스페이서의 형성시 상기 배선이 노출되지 않도록 상기 스페이서의 두께를 조절하는 것을 특징으로 하는 반도체장치의 층간절연막 형성방법.
  3. 제1항에 있어서, 상기 스페이서를 형성하는 단계 후, 상기 스페이서가 형성된 결과물 전면에 하부 절연막을 형성하는 단계; 상기 하부 절연막 상에 스핀-은-글라스를 도포하는 단계; 상기 스핀-은-글라스를 에치백하는 단계; 및 상기 결과물 전면에 상부 절연막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체장치의 층간절연막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940017850A 1994-07-23 1994-07-23 반도체장치의 층간절연막 형성방법 KR0144950B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940017850A KR0144950B1 (ko) 1994-07-23 1994-07-23 반도체장치의 층간절연막 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940017850A KR0144950B1 (ko) 1994-07-23 1994-07-23 반도체장치의 층간절연막 형성방법

Publications (2)

Publication Number Publication Date
KR960005850A true KR960005850A (ko) 1996-02-23
KR0144950B1 KR0144950B1 (ko) 1998-08-17

Family

ID=19388638

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940017850A KR0144950B1 (ko) 1994-07-23 1994-07-23 반도체장치의 층간절연막 형성방법

Country Status (1)

Country Link
KR (1) KR0144950B1 (ko)

Also Published As

Publication number Publication date
KR0144950B1 (ko) 1998-08-17

Similar Documents

Publication Publication Date Title
KR920020619A (ko) 텅스텐플러그의 형성방법
KR960005850A (ko) 반도체장치의 층간절연막 형성방법
KR920017186A (ko) 집적 회로의 도전성 구조
KR960043176A (ko) 캐패시터 제조방법
KR970052381A (ko) 반도체 소자의 금속층 형성 방법
KR970052369A (ko) 반도체 장치의 콘택홀 형성방법
KR930014793A (ko) 반도체 장치의 금속공정
KR960005957A (ko) 다층배선 형성방법
KR970053562A (ko) 반도체 장치의 층간 절연막 형성 방법
KR960002563A (ko) 반도체소자의 콘택홀 형성방법
KR970018411A (ko) 반도체장치의 금속배선층 형성방법
KR960005835A (ko) 반도체 소자의 금속막간 절연 방법
KR960026169A (ko) 콘택 홀 형성 방법
KR960042958A (ko) 반도체 소자의 콘택홀 형성 방법
KR960026191A (ko) 반도체 소자의 금속배선 형성방법
KR970003520A (ko) 미세 반도체 소자의 콘택홀 형성방법
KR970003839A (ko) 반도체장치의 다층 배선구조 및 그 형성방법
KR980005671A (ko) 반도체 장치의 스택콘택 형성방법
KR970052599A (ko) 반도체장치의 식각방법
KR970023756A (ko) 반도체장치의 스페이서 형성방법
KR980005466A (ko) 반도체 장치의 금속배선 형성방법
KR960035981A (ko) 반도체 장치의 금속배선 콘택부 형성방법
KR960019518A (ko) 반도체 소자의 콘택홀 및 그의 형성방법
KR940027071A (ko) 시각베리어층을 이용한 텅스텐 배선 형성방법
KR970072319A (ko) 반도체 장치의 층간절연막 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100413

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee