KR920018851A - 메탈플러그의 형성방법 - Google Patents

메탈플러그의 형성방법 Download PDF

Info

Publication number
KR920018851A
KR920018851A KR1019920004729A KR920004729A KR920018851A KR 920018851 A KR920018851 A KR 920018851A KR 1019920004729 A KR1019920004729 A KR 1019920004729A KR 920004729 A KR920004729 A KR 920004729A KR 920018851 A KR920018851 A KR 920018851A
Authority
KR
South Korea
Prior art keywords
forming
metal plug
connection hole
metal
insulating film
Prior art date
Application number
KR1019920004729A
Other languages
English (en)
Other versions
KR100242865B1 (ko
Inventor
쥰이찌 사또
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920018851A publication Critical patent/KR920018851A/ko
Application granted granted Critical
Publication of KR100242865B1 publication Critical patent/KR100242865B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/02Contacts, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

매탈플러그의 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 메탈플러그의 형성방법의 제1실시예를 도시한 제조공정도(1).
제2도는 본원 발명의 메탈플러그의 형성방법의 제1실시예를 도시한 제조공정도(2).
제3도는 본원 발명의 메탈플러그의 형성방법의 제2실시예를 나타낸 제조공정도(1).

Claims (3)

  1. 절연막의 접속공에 메탈플러그를 형성하는 방법에 있어서, 접속공을 포함하는 상기 절연막상에 밀착층을 통해 메탈을 형성하고, 상기 접속공보다 폭이 넓게 남도록 상기 메탈 및 밀착층을 제거하여 메탈 플러그를 형성하는 것을 특징으로 하는 메탈플러그의 형성 방법.
  2. 절연막의 접속공에 메탈플러그를 형성하는 방법에 있어서, 상부가 하부보다 넓은 상기 접속공을 형성하고, 이 접속공내에 메탈을 매입하여 메탈플러그를 형성하는 것을 특징으로 하는 메탈플러그의 형성방법.
  3. 절연막의 접속공에 메탈플러그를 형성하는 방법에 있어서, 상기 절연막 상에 제1의 메탈에 대한 밀착층을 형성하는 공정과, 상기 밀착층과 함께 상기 절연막에 접속공을 형성하는 공정과, 상기 접속공내의 도중까지 제2의 메탈을 형성하는 공정과, 상기 접속공내를 포함하여 제1의 메탈을 형성하고 에칭하여 상기 제1 및 제2의 메탈에 의한 메탈플러그를 형성하는 공정을 가지는 것을 특징으로 하는 메탈플러그의 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920004729A 1991-03-27 1992-03-23 메탈 플러그의 형성 방법 KR100242865B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-63,463 1991-03-27
JP3063463A JPH04298030A (ja) 1991-03-27 1991-03-27 メタルプラグの形成方法

Publications (2)

Publication Number Publication Date
KR920018851A true KR920018851A (ko) 1992-10-22
KR100242865B1 KR100242865B1 (ko) 2000-02-01

Family

ID=13229959

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920004729A KR100242865B1 (ko) 1991-03-27 1992-03-23 메탈 플러그의 형성 방법

Country Status (3)

Country Link
US (1) US5284799A (ko)
JP (1) JPH04298030A (ko)
KR (1) KR100242865B1 (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130852A (ja) * 1993-11-02 1995-05-19 Sony Corp 金属配線材料の形成方法
KR0129985B1 (ko) * 1993-12-17 1998-04-07 김광호 반도체장치 및 그의 제조방법
US5442235A (en) * 1993-12-23 1995-08-15 Motorola Inc. Semiconductor device having an improved metal interconnect structure
KR0137978B1 (ko) * 1994-10-12 1998-06-15 김주용 반도체 소자 제조방법
US5567650A (en) * 1994-12-15 1996-10-22 Honeywell Inc. Method of forming tapered plug-filled via in electrical interconnection
EP0720227B1 (en) * 1994-12-29 2004-12-01 STMicroelectronics, Inc. Electrical connection structure on an integrated circuit device comprising a plug with an enlarged head
KR100187666B1 (ko) * 1995-02-24 1999-06-01 김주용 반도체 소자의 텅스텐 플러그 형성방법
US5686761A (en) * 1995-06-06 1997-11-11 Advanced Micro Devices, Inc. Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US6294799B1 (en) * 1995-11-27 2001-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating same
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
KR100215846B1 (ko) * 1996-05-16 1999-08-16 구본준 반도체장치의 배선형성방법
KR100186509B1 (ko) * 1996-05-16 1999-04-15 문정환 반도체장치의 배선 형성방법
US5814557A (en) * 1996-05-20 1998-09-29 Motorola, Inc. Method of forming an interconnect structure
JP2800788B2 (ja) * 1996-06-27 1998-09-21 日本電気株式会社 半導体装置の製造方法
JPH10125865A (ja) * 1996-10-15 1998-05-15 Fujitsu Ltd 半導体装置、半導体記憶装置、およびその製造方法
US5981385A (en) * 1997-01-27 1999-11-09 Taiwan Semiconductor Manufacturing Company Ltd. Dimple elimination in a tungsten etch back process by reverse image patterning
US6271117B1 (en) * 1997-06-23 2001-08-07 Vanguard International Semiconductor Corporation Process for a nail shaped landing pad plug
US5989984A (en) * 1997-10-07 1999-11-23 Lucent Technologies, Inc. Method of using getter layer to improve metal to metal contact resistance at low radio frequency power
US6171963B1 (en) * 1998-11-30 2001-01-09 Worldwide Semiconductor Manufacturing Corporation Method for forming a planar intermetal dielectric using a barrier layer
TW454330B (en) * 1999-05-26 2001-09-11 Matsushita Electronics Corp Semiconductor apparatus and its manufacturing method
KR20010112688A (ko) * 2000-06-10 2001-12-21 황인길 메탈 배선 형성 방법
KR100688761B1 (ko) * 2002-12-30 2007-02-28 동부일렉트로닉스 주식회사 반도체의 금속배선 형성방법
DE102004026232B4 (de) * 2004-05-28 2006-05-04 Infineon Technologies Ag Verfahren zum Ausbilden einer integrierten Halbleiterschaltungsanordnung
US7385258B2 (en) * 2006-04-25 2008-06-10 International Business Machines Corporation Transistors having v-shape source/drain metal contacts
TWI403235B (zh) * 2010-07-14 2013-07-21 Taiwan Memory Company 埋藏式電路結構之製作方法
US20180144973A1 (en) * 2016-11-01 2018-05-24 Applied Materials, Inc. Electromigration Improvement Using Tungsten For Selective Cobalt Deposition On Copper Surfaces

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789760A (en) * 1985-04-30 1988-12-06 Advanced Micro Devices, Inc. Via in a planarized dielectric and process for producing same
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device
JPS63311724A (ja) * 1987-06-15 1988-12-20 Toshiba Corp 半導体装置の製造方法
US4981550A (en) * 1987-09-25 1991-01-01 At&T Bell Laboratories Semiconductor device having tungsten plugs
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
US5008730A (en) * 1988-10-03 1991-04-16 International Business Machines Corporation Contact stud structure for semiconductor devices
JPH0793353B2 (ja) * 1988-11-24 1995-10-09 日本電気株式会社 半導体装置の製造方法
US5104826A (en) * 1989-02-02 1992-04-14 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor integrated circuit device using an electrode wiring structure
US5000818A (en) * 1989-08-14 1991-03-19 Fairchild Semiconductor Corporation Method of fabricating a high performance interconnect system for an integrated circuit
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten

Also Published As

Publication number Publication date
US5284799A (en) 1994-02-08
JPH04298030A (ja) 1992-10-21
KR100242865B1 (ko) 2000-02-01

Similar Documents

Publication Publication Date Title
KR920018851A (ko) 메탈플러그의 형성방법
KR880013239A (ko) 반도체소자의 접속구멍형성 방법
KR920018850A (ko) 메탈플러그의 형성방법
KR930001314A (ko) 다층 배선의 형성방법
KR910700533A (ko) 절연 전선
KR920020619A (ko) 텅스텐플러그의 형성방법
KR920010875A (ko) 다층배선의 단차를 완화시키는 방법
KR900013605A (ko) 반도체 기판상의 가용성 링크 제작방법
KR960027004A (ko) 반도체 장치의 측면콘택 형성방법
KR880010495A (ko) 반도체장치의 제조방법
KR920001678A (ko) 금속 배선의 알루미늄 산화막 형성 제조방법
KR970052836A (ko) 더미 배선을 갖춘 반도체 장치 및 그 제조 방법
KR940016503A (ko) 텅스텐을 이용한 콘택플러그 제조방법
KR920010876A (ko) 폴리실리콘층에 금속층 콘택 형성방법
KR920015469A (ko) 메탈 에칭(metal etch)시 메탈 증착방법
KR950034526A (ko) 고부하저항 제조방법
KR920017212A (ko) 트렌치 형성방법
KR920015547A (ko) 반도체소자의 금속배선 형성방법
JPS56104450A (en) Manufacture of semiconductor device
KR950021050A (ko) 웨이퍼의 단차 완화 방법
KR960043029A (ko) 반도체 소자의 금속 배선 형성방법
KR900002432A (ko) 반도체의 사이드벽 형성방법
KR930002877A (ko) 단차가 없는 도전층 패턴 제조방법
KR910001901A (ko) 접촉창 형성 방법
KR940016507A (ko) 반도체 소자의 금속배선 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee