KR900013605A - 반도체 기판상의 가용성 링크 제작방법 - Google Patents

반도체 기판상의 가용성 링크 제작방법 Download PDF

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Publication number
KR900013605A
KR900013605A KR1019900001231A KR900001231A KR900013605A KR 900013605 A KR900013605 A KR 900013605A KR 1019900001231 A KR1019900001231 A KR 1019900001231A KR 900001231 A KR900001231 A KR 900001231A KR 900013605 A KR900013605 A KR 900013605A
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KR
South Korea
Prior art keywords
semiconductor substrate
fusible link
sidewall spacer
manufacturing fusible
manufacturing
Prior art date
Application number
KR1019900001231A
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English (en)
Other versions
KR0146284B1 (ko
Inventor
토마스 마스트로이안니 샐
Original Assignee
빈센트 죠셉 로너만
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 빈센트 죠셉 로너만, 모토로라 인코포레이티드 filed Critical 빈센트 죠셉 로너만
Publication of KR900013605A publication Critical patent/KR900013605A/ko
Application granted granted Critical
Publication of KR0146284B1 publication Critical patent/KR0146284B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/055—Fuse

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 기판상의 가용성 링크 제작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도 및 제 2도는 본 발명 실시 구조의 여러 개발단계를 표시한 확대 단면도,
제 3도는 본 발명의 실시 구조의 확대 단면도,
제 4도는 제 2실시예에 대한 확대 단면도.

Claims (3)

  1. 반도체 기판상에 가용성 링크를 제작하는 방법에 있어서, 상기 반도체 기판상에 절연층을 설치하는 단계와, 상기 절연층과 경계선을 형성시켜서, 이 경계선 주변에 측벽 스페이서가 형성되도록 하는 단계와, 가용성 링크로서의 역할을 할 재질로부터 측벽스페이서를 형성하는 단계를 포함하는 가용성 링크의 제작방법.
  2. 제 1항에 있어서, 형성된 측벽 스페이서의 재질은 금속 재질인 가용성 링크의 제작방법.
  3. 제 1항에 있어서, 형성된 측벽 스페이서의 재질은 폴리실리콘 재질은 가용성 링크의 제작방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900001231A 1989-02-03 1990-02-02 반도체 기판상의 가용성 링크 제조방법 KR0146284B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/305,575 US5011791A (en) 1989-02-03 1989-02-03 Fusible link with built-in redundancy
US305575 1989-02-03
US305,575 1989-02-03

Publications (2)

Publication Number Publication Date
KR900013605A true KR900013605A (ko) 1990-09-06
KR0146284B1 KR0146284B1 (ko) 1998-11-02

Family

ID=23181366

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900001231A KR0146284B1 (ko) 1989-02-03 1990-02-02 반도체 기판상의 가용성 링크 제조방법

Country Status (4)

Country Link
US (1) US5011791A (ko)
EP (1) EP0445317B1 (ko)
JP (1) JPH02265259A (ko)
KR (1) KR0146284B1 (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0509631A1 (en) * 1991-04-18 1992-10-21 Actel Corporation Antifuses having minimum areas
US5557136A (en) * 1991-04-26 1996-09-17 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5701027A (en) * 1991-04-26 1997-12-23 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5196724A (en) * 1991-04-26 1993-03-23 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5120679A (en) * 1991-06-04 1992-06-09 Vlsi Technology, Inc. Anti-fuse structures and methods for making same
US5244836A (en) * 1991-12-30 1993-09-14 North American Philips Corporation Method of manufacturing fusible links in semiconductor devices
US5472901A (en) * 1994-12-02 1995-12-05 Lsi Logic Corporation Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps
US5925920A (en) * 1996-06-12 1999-07-20 Quicklogic Corporation Techniques and circuits for high yield improvements in programmable devices using redundant routing resources
US6175145B1 (en) * 1997-07-26 2001-01-16 Samsung Electronics Co., Ltd. Method of making a fuse in a semiconductor device and a semiconductor device having a fuse
US6222244B1 (en) 1998-06-08 2001-04-24 International Business Machines Corporation Electrically blowable fuse with reduced cross-sectional area
US6524941B2 (en) 1998-06-08 2003-02-25 International Business Machines Corporation Sub-minimum wiring structure
US6580144B2 (en) * 2001-09-28 2003-06-17 Hewlett-Packard Development Company, L.P. One time programmable fuse/anti-fuse combination based memory cell
US6611039B2 (en) * 2001-09-28 2003-08-26 Hewlett-Packard Development Company, L.P. Vertically oriented nano-fuse and nano-resistor circuit elements
EP1576667B1 (en) * 2002-12-16 2012-02-15 Nxp B.V. Poly-silicon stringer fuse

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
JPS59220952A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
JPS6044829B2 (ja) * 1982-03-18 1985-10-05 富士通株式会社 半導体装置の製造方法
US4542577A (en) * 1982-12-30 1985-09-24 International Business Machines Corporation Submicron conductor manufacturing
JPS63237441A (ja) * 1987-03-25 1988-10-03 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPH02265259A (ja) 1990-10-30
EP0445317A1 (en) 1991-09-11
EP0445317B1 (en) 1997-03-05
US5011791A (en) 1991-04-30
KR0146284B1 (ko) 1998-11-02

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