KR910008821A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR910008821A
KR910008821A KR1019900016413A KR900016413A KR910008821A KR 910008821 A KR910008821 A KR 910008821A KR 1019900016413 A KR1019900016413 A KR 1019900016413A KR 900016413 A KR900016413 A KR 900016413A KR 910008821 A KR910008821 A KR 910008821A
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South Korea
Prior art keywords
semiconductor substrate
insulating layer
etching
forming
portions
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KR1019900016413A
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English (en)
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KR930010986B1 (ko
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요시오 바바
유타카 고시노
아키히코 오사와
사토시 야나기야
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아오이 죠이치
가부시키가이샤 도시바
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Publication of KR910008821A publication Critical patent/KR910008821A/ko
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Publication of KR930010986B1 publication Critical patent/KR930010986B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1a∼f도는 본 발명의 일실시예 방법의 주요한 공정을 나타낸 단면도.

Claims (2)

  1. 제1의 반도체기판(1)의 표면상에 제1의 절연층(2)을 매개해서 제2의 반도체기판(3)을 접착하는 공정과, 상기 제2의 반도체기판(3)의 표면상에 제2의 절연층(4)을 형성하는 공정, 상기 제2의 절연층(4)을 패터닝해서 개구부를 갖춘 마스크를 형성하는 공정, 상기 마스크를 이용해서 상기 제2의 반도체기판(3)을 에칭하여 상기 제1의 절연층(2)에 이르는 홈부(5)를 형성하는 공정, 상기 제2의 절연층(4)으로 이루어진 마스크를 에칭하여 상기 개구부의 형상을 크게 함과 더불어 상기 홈부(5)에서 노출되어 있는 상기 제1의 절연층(2)을 동시에 에칭하여 그홈부(5)에 접하는 상기 제2의 반도체기판(3)의 상부 및 저부의 각이진 부분(6,7)을 노출시키는 공정, 등방성 에칭기술로 상기 제2의 반도체기판(3)의 상부 및 저부의 각이진 부분(6,7)을 에칭하여 그 양 각이진 부분(6,7)이 원호형상으로 움푹 파여지게 형성하는 공정 및, 열산화법으로 상기 홈부(5)에서 노출되어 있는 상기 제2의 반도체기판(3) 표면을 산화시켜 그 홈부(5)의 내벽부에 상기 제1의 절연층(2)과 접하는 제3의 절연층(8)을 형성하여 상기 제2의 반도체기판(3)을 상기 홈부(5)로 절연 분리하는 공정을 구비하여 구성된 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 제2의 절연층(4)으로 이루어진 마스크를 에칭하여 상기 개구부의 형상을 크게 할 때의 에칭량이 3000Å 보다도 크고, 또 상기 제2의 반도체기판의 상부 및 저부의 각이진 부분(6,7)을 에칭할 때의 에칭량이 2000Å 전후인 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900016413A 1989-10-16 1990-10-16 반도체장치의 제조방법 KR930010986B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1268544A JPH03129854A (ja) 1989-10-16 1989-10-16 半導体装置の製造方法
JP1-268544 1989-10-16
JP89-268544 1989-10-16

Publications (2)

Publication Number Publication Date
KR910008821A true KR910008821A (ko) 1991-05-31
KR930010986B1 KR930010986B1 (ko) 1993-11-18

Family

ID=17460006

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016413A KR930010986B1 (ko) 1989-10-16 1990-10-16 반도체장치의 제조방법

Country Status (5)

Country Link
US (1) US5084408A (ko)
EP (1) EP0423722B1 (ko)
JP (1) JPH03129854A (ko)
KR (1) KR930010986B1 (ko)
DE (1) DE69033595T2 (ko)

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Also Published As

Publication number Publication date
JPH03129854A (ja) 1991-06-03
KR930010986B1 (ko) 1993-11-18
US5084408A (en) 1992-01-28
DE69033595D1 (de) 2000-08-24
JPH0580148B2 (ko) 1993-11-08
EP0423722B1 (en) 2000-07-19
EP0423722A3 (en) 1993-01-13
EP0423722A2 (en) 1991-04-24
DE69033595T2 (de) 2001-03-08

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