IT1040004B - Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore - Google Patents

Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore

Info

Publication number
IT1040004B
IT1040004B IT2568975A IT2568975A IT1040004B IT 1040004 B IT1040004 B IT 1040004B IT 2568975 A IT2568975 A IT 2568975A IT 2568975 A IT2568975 A IT 2568975A IT 1040004 B IT1040004 B IT 1040004B
Authority
IT
Italy
Prior art keywords
lathes
marginal
slab
creation
semiconductor material
Prior art date
Application number
IT2568975A
Other languages
English (en)
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Application granted granted Critical
Publication of IT1040004B publication Critical patent/IT1040004B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)
IT2568975A 1974-08-21 1975-07-23 Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore IT1040004B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49928874A 1974-08-21 1974-08-21

Publications (1)

Publication Number Publication Date
IT1040004B true IT1040004B (it) 1979-12-20

Family

ID=23984661

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2568975A IT1040004B (it) 1974-08-21 1975-07-23 Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore

Country Status (7)

Country Link
JP (1) JPS5146076A (it)
BE (1) BE832633A (it)
CA (1) CA1038969A (it)
DE (1) DE2536108A1 (it)
FR (1) FR2282722A1 (it)
GB (1) GB1471116A (it)
IT (1) IT1040004B (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7607298A (nl) * 1976-07-02 1978-01-04 Philips Nv Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze.
FR2410366A1 (fr) * 1977-11-29 1979-06-22 Radiotechnique Compelec Transistor de type mesa et procede de realisation de ce transistor
JPS5895553A (ja) * 1981-12-01 1983-06-07 Nippon Shokubai Kagaku Kogyo Co Ltd 耐熱衝撃性の改良されたハニカム触媒の製造方法
DE3422051C2 (de) * 1984-06-14 1986-06-26 Brown, Boveri & Cie Ag, 6800 Mannheim Silizium-Halbleiterbauelement mit ätztechnisch hergestellter Randkontur und Verfahren zur Herstellung dieses Bauelements
GB2176338A (en) * 1985-06-06 1986-12-17 Marconi Electronic Devices Edge contouring in a semiconductor device
JPH0777240B2 (ja) * 1989-01-20 1995-08-16 富士通株式会社 半導体装置の製造方法
JPH03129854A (ja) * 1989-10-16 1991-06-03 Toshiba Corp 半導体装置の製造方法
DE19536438A1 (de) * 1995-09-29 1997-04-03 Siemens Ag Halbleiterbauelement und Herstellverfahren

Also Published As

Publication number Publication date
GB1471116A (en) 1977-04-21
CA1038969A (en) 1978-09-19
FR2282722A1 (fr) 1976-03-19
JPS5227033B2 (it) 1977-07-18
BE832633A (fr) 1975-12-16
DE2536108A1 (de) 1976-03-11
JPS5146076A (ja) 1976-04-20

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