IT1040004B - Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore - Google Patents
Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttoreInfo
- Publication number
- IT1040004B IT1040004B IT25689/75A IT2568975A IT1040004B IT 1040004 B IT1040004 B IT 1040004B IT 25689/75 A IT25689/75 A IT 25689/75A IT 2568975 A IT2568975 A IT 2568975A IT 1040004 B IT1040004 B IT 1040004B
- Authority
- IT
- Italy
- Prior art keywords
- lathes
- marginal
- slab
- creation
- semiconductor material
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US49928874A | 1974-08-21 | 1974-08-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT1040004B true IT1040004B (it) | 1979-12-20 |
Family
ID=23984661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT25689/75A IT1040004B (it) | 1974-08-21 | 1975-07-23 | Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS5146076A (it) |
| BE (1) | BE832633A (it) |
| CA (1) | CA1038969A (it) |
| DE (1) | DE2536108A1 (it) |
| FR (1) | FR2282722A1 (it) |
| GB (1) | GB1471116A (it) |
| IT (1) | IT1040004B (it) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7607298A (nl) * | 1976-07-02 | 1978-01-04 | Philips Nv | Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze. |
| FR2410366A1 (fr) * | 1977-11-29 | 1979-06-22 | Radiotechnique Compelec | Transistor de type mesa et procede de realisation de ce transistor |
| JPS5895553A (ja) * | 1981-12-01 | 1983-06-07 | Nippon Shokubai Kagaku Kogyo Co Ltd | 耐熱衝撃性の改良されたハニカム触媒の製造方法 |
| DE3422051C2 (de) * | 1984-06-14 | 1986-06-26 | Brown, Boveri & Cie Ag, 6800 Mannheim | Silizium-Halbleiterbauelement mit ätztechnisch hergestellter Randkontur und Verfahren zur Herstellung dieses Bauelements |
| GB2176338A (en) * | 1985-06-06 | 1986-12-17 | Marconi Electronic Devices | Edge contouring in a semiconductor device |
| JPH0777240B2 (ja) * | 1989-01-20 | 1995-08-16 | 富士通株式会社 | 半導体装置の製造方法 |
| JPH03129854A (ja) * | 1989-10-16 | 1991-06-03 | Toshiba Corp | 半導体装置の製造方法 |
| DE19536438A1 (de) * | 1995-09-29 | 1997-04-03 | Siemens Ag | Halbleiterbauelement und Herstellverfahren |
-
1975
- 1975-07-23 CA CA232,120A patent/CA1038969A/en not_active Expired
- 1975-07-23 IT IT25689/75A patent/IT1040004B/it active
- 1975-08-12 GB GB3354775A patent/GB1471116A/en not_active Expired
- 1975-08-13 DE DE19752536108 patent/DE2536108A1/de active Pending
- 1975-08-19 FR FR7525662A patent/FR2282722A1/fr not_active Withdrawn
- 1975-08-20 JP JP50101658A patent/JPS5146076A/ja active Granted
- 1975-08-21 BE BE159371A patent/BE832633A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| FR2282722A1 (fr) | 1976-03-19 |
| GB1471116A (en) | 1977-04-21 |
| JPS5146076A (en) | 1976-04-20 |
| CA1038969A (en) | 1978-09-19 |
| JPS5227033B2 (it) | 1977-07-18 |
| DE2536108A1 (de) | 1976-03-11 |
| BE832633A (fr) | 1975-12-16 |
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