GB2176338A - Edge contouring in a semiconductor device - Google Patents

Abstract

A semiconductor device is provided with a recess (20) which intersects a pn junction (2) and is so shaped as to enhance the ability of the device to withstand high reverse bias voltages without breakdown. The recess is provided with two steps meeting at a knee (23) between the point (27) at which the pn junction intersects the recess and the surface of the device itself. The breakdown potential can be significantly increased as compared with a conventional single step recess. <IMAGE>

Description

SPECIFICATION Semiconductor devices This invention relates to semiconductor devices and is particularly concerned with improving the resistance to voltage breakdown which can occur when a high voltage is present across a pn junction. When a pn junction is reverse biased, a charge depletion region develops, and in many instances the voltage difference which the depletion region can withstand is greater than that at which surface breakdown occurs. It is customary to contour the surface of the semiconductor where the pn junction meets it in order to keep the electrical field strength as low as possible. Even so, the results which are achievable can result in voltage breakdown occurring at a surface in a manner which limits the usefulness of a semiconductor device. The present invention seeks to provide an improved semiconductor device.

According to a first aspect of this invention a body of semiconductor material includes a pn junction which extends to a multi-step recess formed in the surface of said body such that in operation the charge depletion region of said pn junction extends to both sides of a knee which is positioned between two adjacent steps of said recess.

According to a second aspect of this invention a semiconductor device includes a pn junction lying substantially parallel to a major surface of a semiconductor body in which it is formed such that it intersests a double-step recess extending into said body from said surface, the recess having a knee which is positioned between said surface and the position at which the recess is intersected by said pn junction.

Preferably the recess is provided with a floor portion which is positioned between the knee and said surface and which is at least approximately parallel to the pn junction, and the recess is provided with a steep curved side wall portion at the position where it is intersected by said pn junction.

The multi-step recess forms a tier above the knee which not only increases the physical distance across the charge depletion region where it meets the recess, but also the knee and the floor portion serve to distribute the potential difference across the whole distance thereby minimising the risk of producing locaiised high electrical field strengths which could initiate surface voltage breakdown. The recess may take the form of a groove set into the surface at the edge of a semiconductor device or as part of the peripheral edge of a device.

The recess can be used as a convenient means of passivating the exposed pn junction by partially or wholly covering the surface of the recess with an electrically insulating passivation material. If the recess is in the form of a groove it may be of a symmetrical nature with steps on both internal side walls, or it may be asymmetrical with the knee formed only on one internal side wall at which protection against voltage breakdown is required.

In practice, the peak field strength is dependent on the actual mean position of the pn junction with respect to the knee, and by correctly dimensioning the recess in relation to the surface of the semiconductor body and the pn junction, resistance to voltage breakdown can be maximised, although even if its position is not optimised it is believed that the voltage at which surface breakdown occurs will be at least as great as, if not greater, than that obtained from a conventional single step recess.

The invention is further described by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a sectional view through semiconductor body having a conventional single step recess, Figure 2 illustrates a semiconductor body having a multi-step recess in accordance with the invention, and Figure 3 is an explanatory diagram illustrating electric potential distributions.

Referring to Figure 1, there is shown therein a known arrangement in which a body 1 of semiconductor material has a pn junction 2 formed between the region 3 of n type silicon which constitutes the bulk of the body 1 and a surface layer region 4 of p type material formed by the introduction of a suitable dopant. A single step recess 5 is formed at the surface 6 of the body 1 so as to intersect the pn junction 2 at intersection 7. In operation, the pn junction 2 is required to withstand a very high reverse bias which may be applied across it. In ccnventional manner a charge depletion region, the boundaries 8 and 9 of which are represented by the broken lines is formed when the junction 2 is reverse biased, and the recess 5 is so shaped as to minimise the peak electric field strength which results.

By such means the likelihood of voltage breakdown can be reduced to a certain extent.

However, the degree of protection given by such a recess can be very much less than is desired and it may necessitate the operation of high voltage semiconductor devices at rather lower voltages than would otherwise be the case. In a typical example, the overall width of the recess 5 is 400 microns and the overall depth is about 120 microns, whereas the distance between the surface 6 and the mean level of the pn junction 2 may be only 85 microns. In practice, the recess 5 is formed by a conventional chemical etching process in which the bulk of the surface 6 is masked against the action of an etchant which removes part of the silicon so as to leave a recess having a smoothly curved internal surface as shown.

Typically, the silicon bocy 1 is in the shape of a large area wafer on which a considerable number of separate semiconductor devices are formed, an array of two sets of crossing recesses or grooves serving to divide the wafer into a mosaic of island regions. Subsequently the island regions are separated adjacent to the bases of the recesses typical separation line is indicated by numeral 12-to prcduce a large number of separate small devices.

With reference to Figure 2, there is shown therein a semiconductor device in accordance with the invention in which the recess 20 is formed as a multi-stepped recess so as to enhance the resistance to voltage breakdown.

Those parts of Figure 2 which correspond to Figure 1 are given like reference numerals, and it will be seen that the overall depth of the pn junction 2 and the overall width of the recess 20 are the same as for the original reoess 5.

In this instance, the left hand wall of the recess 20 is provided with two steps, a lower step portion 21 and an upper step portion 22 which are separated by an intervening knee 23 which is positioned just above the pn junction 2 which intersects the recess at a steep curved wall portion 27.

When the junction 2 is reversed biased, the charge depletion region extends between the two boundaries 8 and 9, and it will be seen that these lines curve in a characteristic fashion at the point where they meet the surface of the recess 20. The step 22 has a side wall portion 24 and a flatish floor portion 25 which is approximately parallel with the pn junction 2.

The position of the junction 2 with respect to the floor portion 25 and the knee 23 affects to a considerable extent the peak electric field strength which is present, thereby determining the voltage at which voltage breakdown occurs at the surface of the charge depletion region. In Figure 2, the recess is asymmetrical, i.e. a knee 23 is present in only one side thereof, but it may be symmetrical with a knee in both sides if required.

Figure 3 illustrates part of the recess shown in Figure 2 in greater detail. The heavy line 30 represents the material boundary of the semiconductor material and the heavy broken line 31 is the pn junction boundary between the regions 3 and 4 of the semiconductor material. The thin solid lines superimposed upon this structure represent lines of electric equipotentials. It will be seen that the lines are evenly spaced and this means that the potential difference existing across the junction 31 is spread uniformly across the distance at which the charge depletion region extends over the surface of the recess.

It is found that if the knee 23 and the flat floor portion 25 are closer to the junction 2, or further away from the junction 2 than an optimum distance, then the figure at which voltage breakdown occurs is reduced somewhat.

By way of example, it should be noted that the typical breakdown figure for the single groove illustrated in Figure 1, is of the order of 1,000 volts, whereas for a recess having overall similar dimensions the profile shown in Figure 2 enables a breakdown voltage of 1200 volts to be readily obtained and this can rise to as high as 1600 volts if the junction is very carefully positioned with respect to the knee 23.

The double-step recess of Figure 2 can conveniently be formed by an etch process in which the shallower portion 26 having the floor portion 25 is first etched using a simple mask in the conventional manner so that in effect, a shallower version of the recess shown in Figure 1 is formed, which defines the whole width of the recess 20. The depth of this recess is such that it extends slightly above the position of the pn junction 2. Subsequently, a narrower mask and a deeper etch process is used, so as to produce the required profile of the second step region 21 having the wall portion 27 and to leave the knee 23 at the point where the second deeper etch intersects the first shallower etch. Both steps of the recess are partially or completely filled with an inert non-conductive passivation material.Suitable vapour deposition techniques can be used, and the passivation of the whole of the surface area of the charge depletion region considerably enhances the electrical operation. A large number of recesses in crossing relationship can be formed to leave a mosaic of individual semiconductor devices which can be separated adjacent to the bases of the recesses, e.g. along line 12. In this instance symmetrical double step recesses are preferred. Thus, each of the individual semiconductor devices will be bounded by a peripheral edge which is constituted by the double-step recess. This considerably enhances the resistance to surface breakdown when high reverse bias potentials are applied. The application of the passivation material to the double step re -cess, whilst the semiconductor devices are still part of the same semiconductor body, considerably eases manufacturing techniques and enhances the reliability and practicality of the process. The resulting large number of small semiconductor devices have closely controlled characteristics with consistant voltage breakdown properties.

Claims (7)

1. A body of semiconductor material including a pn junction which extends to a multistep recess formed in the surface of said body such than in operation the charge depletion region of said pn junction extends to both sides of a knee which is positioned between two adjacent steps of said recess.

2. A semiconductor device including a pn junction lying substantially parallel to a major surface of a semiconductor body in which it is formed such that it intersects a double-step recess extending into said body from said surface, the recess havng a knee which is positioned between said surface and the position at which the recess is intersected by said pn junction.

3. A device as in claim 1 and wherein the recess is provided with a floor portion which is positioned between the knee and said surface and which is at least approximately parallel to the pn junction, and the recess is provided with a steep curved side wall portion at the position where it is intersected by the pn junction,

4. A device as claimed in claim 2 or 3 and wherein the recess is formed by the use of two sequential etch processes to remove semiconductor material.

5. A device as claimed in claim 4 and wherein a shallower portion of the recess is formed by the first etch process, and a deeper portion of the recess is formed by the second etch process, the knee being formed at the intersection of the two portions.

6. A device as claimed in claim 2, 3, 4 or 5 and wherein the device is completely bounded by a peripheral edge which includes the double-step recess.

7. A device substantially as illustrated in and described with reference to Figure 2 of the accompanying drawing.