JP4048628B2 - Trench type MOS semiconductor device - Google Patents

Trench type MOS semiconductor device Download PDF

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Publication number
JP4048628B2
JP4048628B2 JP00041599A JP41599A JP4048628B2 JP 4048628 B2 JP4048628 B2 JP 4048628B2 JP 00041599 A JP00041599 A JP 00041599A JP 41599 A JP41599 A JP 41599A JP 4048628 B2 JP4048628 B2 JP 4048628B2
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Japan
Prior art keywords
trench
conductivity type
oxide film
channel region
semiconductor device
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JP00041599A
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JP2000200901A (en
Inventor
武義 西村
岳志 堤
勇一 小野沢
和俊 杉村
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明は、トレンチ内に絶縁膜を介して埋め込まれた制御用のゲート電極を有する、ＭＯＳＦＥＴ（金属−酸化膜−半導体構造のゲート電極を有する電界効果トランジスタ）、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）、絶縁ゲートサイリスタ、およびそれらの集合体であるインテリジェントパワーモジュール（ＩＰＭ）などのトレンチ型ＭＯＳ半導体装置に関する。
【０００２】
【従来の技術】
図４（ａ）は、従来のトレンチ構造を有するＭＯＳ半導体装置の一例であるＭＯＳＦＥＴの主要部の透視平面図、同図（ｂ）は図４（ａ）でのＡ−Ａ線に沿った部分断面図、同図（ｃ）は同様にＢ−Ｂ線に沿った部分断面図である。
図４（ａ）において、５はトレンチ、１７はフィールド酸化膜２のエッジであり、１６はゲート電極４を掘り下げたステップである。
【０００３】
図４（ｂ）において、ｎ+ 型ドレイン層６ａとｎ型ドリフト層６ｂからなる半導体基板１の、ｎ型ドリフト層６ｂの表面層にｐ型チャネル領域７が形成され、そのｐ型チャネル領域７の表面層にｎ型ソース領域８が形成されている。ｎ型ソース領域８の表面からｐ型チャネル領域７を貫通してｎ型ドリフト層６ｂに達するトレンチ５が形成され、そのトレンチ５の内部には、ゲート酸化膜３を挟んで多結晶シリコンからなるゲート電極４が充填されている。ｎ型ソース領域８の表面上には、（図示しないがｎ型ソース領域８を貫通してｐ型チャネル領域７に達する孔が分散して形成されていて、）ｐ型チャネル領域７にも共通に接触するソース電極９が、またｎ+ 型ドレイン層６ａの裏面にはドレイン電極１０が設けられている。１１はゲート電極４を覆う絶縁膜である。
【０００４】
図４（ｃ）に示すように、トレンチ５の終端部は、ゲート電極４の引出し部にもなっており、ゲート電極４は、半導体基板１の表面上に延長され、フィールド酸化膜２上でゲート金属電極１３と接続されている。
【０００５】
このゲート金属電極１３に適当な電圧を印加することにより、トレンチ５の内壁に沿ったｐ型チャネル領域７の表面層に反転層（チャネル）を生じ、ドレイン電極１０とソース電極９間が導通して電流が流れる。この例のように、絶縁膜１１の上にソース電極９が延長されることが多いが、このようにしなければならないわけではない。
【０００６】
【発明が解決しようとする課題】
図４（ｄ）は、トレンチ溝終端部の拡大断面図である。この図に見られるように、ゲート電極４と半導体基板１とはゲート酸化膜３で絶縁されている。トレンチ５は、通常ドライエッチングで形成されるがその際、トレンチ５の終端部では、上角部１４で尖り、そのためゲート酸化膜３が薄くなったり、電界が集中したりして、ゲート酸化膜３の耐圧低下を招くことがあった。例えば、図の場合、上角部１４でゲート酸化膜３の厚さが約３０％薄くなっている。そして、この終端上角部１４の尖端は、図４（ａ）のトレンチ５のコーナー部１８で最も鋭くなり、コーナー部１８の曲率半径が小さくなる程鋭くなることが知られている。
【０００７】
この問題の対策として、例えばトレンチ５の終端上角部１４の角を削り、或いは、その部分のゲート酸化膜３を厚くするなどの方法が、特開平７−２４９７６９号公報に開示されている。しかし、その開示された方法では、トレンチ５の終端上角部１４を削り落とし、もしくはこの部分のゲート酸化膜３を厚くするための工程を加えなければならない。また、例えそのような工程を加えたとしてもトレンチ５のコーナー部１８で最も鋭くなることに変わりは無い。
【０００８】
以上の問題に鑑み本発明の目的は、ゲート酸化膜の耐圧低下を防止し、しかも製造が容易なトレンチ構造を有するトレンチ型ＭＯＳ半導体装置を提供することにある。
【０００９】
【課題を解決するための手段】
上記課題解決のため本発明は、第一導電型ドレイン層と、その第一導電型ドレイン層上に設けられた第二導電型チャネル領域と、第二導電型チャネル領域の表面層に形成された第一導電型ソース領域と、その第一導電型ソース領域の表面から第二導電型チャネル領域を貫通し第一導電型ドレイン層に達するトレンチと、トレンチ内にゲート絶縁膜を介して設けられたゲート電極層と、第一導電型ソース領域と第二導電型チャネル領域との表面に共通に接触して設けられたソース電極と、第一導電型ドレイン層に接触して設けられたドレイン電極とからなるトレンチ型ＭＯＳ半導体装置において、トレンチの終端に半導体基板の平面方向で円状でトレンチ幅より広い拡大終端部を設け、隣接するトレンチの拡大終端部の位置をトレンチの長手方向にずらした千鳥状とする。
【００１０】
【００１１】
そのようにすれば、トレンチの終端部上角部でのゲート酸化膜の薄膜化が抑制される。
さらに、隣接するトレンチの終端に設ける拡大終端部の位置をトレンチの長手方向に千鳥状にずらすので、拡大終端部の幅を広くすることができる。
【００１２】
【発明の実施の形態】
以下、実施例にもとづき、図を参照しながら本発明の実施の形態を説明する。
［参考例１］
図１は、本発明第一の参考例のＭＯＳＦＥＴの主要部の平面図である。図に示した主要部以外に、主に周縁領域に耐圧を分担する部分があるが、本発明の本質に係る部分でないので、省略している。
【００１３】
図４（ａ）の従来のＭＯＳＦＥＴと比較して異なっているのは、隣のトレンチ溝同士を曲率をつけたトレンチ連結部５１で繋ぎ、終端が無いようになっている点である。例えばトレンチ連結部５１の幅はトレンチ５と同じく１．２μｍ、深さ３μｍ、トレンチ間隔は２．８μｍ、トレンチ連結部５１の外周の曲率半径は２．６μｍである。１７はフィールド酸化膜２のエッジ、１６はゲート電極のステップである。フィールド酸化膜２の厚さは約４５０ｎｍ、半導体基板上のゲート電極４の厚さは約８００ｎｍである。
このようにすることによって、従来のようなトレンチ５の終端上角部での尖端化を抑制し、その部分でのゲート酸化膜３の薄膜化を防止することができる。
【００１４】
実際に試作したトレンチ型ＭＯＳＦＥＴにおいても、ゲート酸化膜の厚さを１００ｎｍとしたとき、ゲート酸化膜の耐圧は、９０Ｖ以上であり、従来の７０Ｖより約３０％向上した。しかも、トレンチ５を形成するためのエッチングマスクを変更するだけで済み、特開平７−２４９７６９号公報の例のような特別な工程の付加を要しない。
【００１５】
［参考例２］
図２は、本発明第二の参考例のＭＯＳＦＥＴの主要部の平面図である。
この例では、トレンチ５の終端にトレンチ５より幅の広い円状の拡大終端部５２を設けている。例えばトレンチ５の幅は１．２μｍ、トレンチ間隔が２．８μｍ、拡大終端部５２の直径は２．８μｍである。
【００１６】
トレンチ５の幅が１．２μｍのとき、従来のトレンチではコーナー部の曲率半径は、大きくしても最大０．６μｍであるが、この参考例ではそれより曲率半径を１．４μｍと倍以上に大きくしたことによって、トレンチの終端上角部の尖端化が抑えられ、ゲート酸化膜３の耐圧を向上させることができる。
【００１７】
実際に試作したトレンチＭＯＳＦＥＴにおいても、ゲート酸化膜の厚さが１００ｎｍのとき、ゲート酸化膜の耐圧は、８４Ｖ以上であり、従来の７０Ｖより約２０％向上した。
【００１８】
拡大終端部５２の直径は最大、トレンチ幅とトレンチ間隔との和に近い値まで可能である。
この場合も、トレンチエッチングのためのマスクパターンを変更するだけで良く、特別に工程数を増やす必要が無い。
【００１９】
［実施例１］
図３は、本発明第一の実施例のＭＯＳＦＥＴの主要部の平面図である。
この例では、トレンチ５の終端にトレンチ５より幅の広い円状の拡大終端部５２を設けているのは参考例２と同じであるが、拡大周端部５２の位置が隣接するトレンチで千鳥状にずらされている点が異なっている。このようにすることにより、拡大終端部５２の直径を４．８μｍと大きくしている。
【００２０】
この場合もトレンチ終端の曲率半径を更に大きくしたことにより、終端上角部の尖端化を抑え、ゲート酸化膜の耐圧を更に向上させることができる。
実際に試作したトレンチＭＯＳＦＥＴにおいて、ゲート酸化膜の耐圧は、９０Ｖ以上であった。
【００２１】
拡大周端部５２の位置を千鳥状にずらした場合は、拡大終端部５２の直径は最大、トレンチ幅とトレンチ間隔との和の２倍に近い値まで可能である。なお、拡大終端部の形状は、円状に限らず、環状、楕円状、楕円環状等でも良いことは云うまでも無い。
【００２２】
実施例はいずれもＭＯＳＦＥＴの例を示したが、ＩＧＢＴ、絶縁ゲートサイリスタ、およびそれらの集合体であるＩＰＭなどのトレンチ型ＭＯＳ半導体装置にも適用できる。
【００２３】
【発明の効果】
以上説明したように本発明によれば、トレンチの終端に半導体基板の平面方向で円状でトレンチ幅より広い拡大終端部を設け、隣接するトレンチの拡大終端部の位置をトレンチの長手方向にずらした千鳥状とすることで、従来問題であったトレンチ終端の上角部の尖り、およびそれによるゲート酸化膜の薄膜化の問題を回避することにより、ゲート酸化膜の耐圧を容易に向上させることができる。
【００２４】
本発明のトレンチ型ＭＯＳ半導体装置の製造方法としては、トレンチ形成用のエッチングマスクを変更するだけで、特に工程を増やすことがなく、極めて容易に実現できる。
【図面の簡単な説明】
【図１】 本発明参考例１のＭＯＳＦＥＴの平面図
【図２】 本発明参考例２のＭＯＳＦＥＴの平面図
【図３】 本発明実施例１のＭＯＳＦＥＴの平面図
【図４】 （ａ）は従来のＭＯＳＦＥＴの平面図、（ｂ）は（ａ）のＡ−Ａ線に沿った断面図、（ｃ）は（ａ）のＢ−Ｂ線に沿った断面図、（ｄ）はトレンチ終端部の拡大断面図
【符号の説明】
１ 半導体基板
２ フィールド酸化膜
３ ゲート酸化膜
４ ゲート電極
５ トレンチ
６ａ ｎ+ 型ドレイン層
６ｂ ｎ型ドリフト層
７ ｐ型チャネル領域
８ ｎ型ソース領域
９ ソース電極
１０ ドレイン電極
１１ 絶縁膜
１３ ゲート金属電極
１４ トレンチ終端の上角部
１６ ゲート電極ステップ
１７ フィールド酸化膜エッジ
１８ トレンチのコーナー部
５１ トレンチ連結部
５２ 拡大終端部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOSFET (field effect transistor having a gate electrode of a metal-oxide film-semiconductor structure), an IGBT (insulated gate bipolar transistor) having a control gate electrode embedded in an insulating film through an insulating film, The present invention relates to an insulated gate thyristor and a trench type MOS semiconductor device such as an intelligent power module (IPM) which is an aggregate thereof.
[0002]
[Prior art]
4A is a perspective plan view of the main part of a MOSFET which is an example of a MOS semiconductor device having a conventional trench structure, and FIG. 4B is a portion along the line AA in FIG. 4A. Sectional drawing and the same figure (c) are partial sectional views which followed the BB line similarly.
In FIG. 4A, 5 is a trench, 17 is an edge of the field oxide film 2, and 16 is a step in which the gate electrode 4 is dug down.
[0003]
In FIG. 4B, a p-type channel region 7 is formed on the surface layer of the n-type drift layer 6b of the semiconductor substrate 1 composed of the n + -type drain layer 6a and the n-type drift layer 6b. An n-type source region 8 is formed in the surface layer. A trench 5 is formed from the surface of the n-type source region 8 through the p-type channel region 7 to reach the n-type drift layer 6b. The trench 5 is made of polycrystalline silicon with the gate oxide film 3 interposed therebetween. The gate electrode 4 is filled. Common to the p-type channel region 7 (on the surface of the n-type source region 8, although not shown, holes that penetrate the n-type source region 8 and reach the p-type channel region 7 are dispersed). The drain electrode 10 is provided on the back surface of the n + -type drain layer 6a. Reference numeral 11 denotes an insulating film that covers the gate electrode 4.
[0004]
As shown in FIG. 4C, the end portion of the trench 5 is also a lead portion of the gate electrode 4, and the gate electrode 4 is extended on the surface of the semiconductor substrate 1 and on the field oxide film 2. A gate metal electrode 13 is connected.
[0005]
By applying an appropriate voltage to the gate metal electrode 13, an inversion layer (channel) is formed in the surface layer of the p-type channel region 7 along the inner wall of the trench 5, and the drain electrode 10 and the source electrode 9 are electrically connected. Current flows. As in this example, the source electrode 9 is often extended on the insulating film 11, but this is not necessarily the case.
[0006]
[Problems to be solved by the invention]
FIG. 4D is an enlarged cross-sectional view of the trench groove end portion. As seen in this figure, the gate electrode 4 and the semiconductor substrate 1 are insulated by a gate oxide film 3. The trench 5 is usually formed by dry etching. At this time, the end portion of the trench 5 is sharp at the upper corner portion 14, so that the gate oxide film 3 is thinned or the electric field is concentrated. 3 may cause a decrease in breakdown voltage. For example, in the case of the figure, the thickness of the gate oxide film 3 is reduced by about 30% at the upper corner portion 14. It is known that the tip of the upper end corner 14 is sharpest at the corner 18 of the trench 5 in FIG. 4A and becomes sharper as the radius of curvature of the corner 18 decreases.
[0007]
As a countermeasure against this problem, for example, a method of cutting the corner of the upper end corner 14 of the trench 5 or increasing the thickness of the gate oxide film 3 is disclosed in Japanese Patent Laid-Open No. 7-249769. However, in the disclosed method, it is necessary to add a step for scraping off the upper end corner portion 14 of the trench 5 or increasing the thickness of the gate oxide film 3 in this portion. Even if such a process is added, the corner portion 18 of the trench 5 is still sharpest.
[0008]
In view of the above problems, an object of the present invention is to provide a trench type MOS semiconductor device having a trench structure that prevents a breakdown voltage of a gate oxide film from being lowered and is easy to manufacture.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is formed in a first conductivity type drain layer, a second conductivity type channel region provided on the first conductivity type drain layer, and a surface layer of the second conductivity type channel region. A first conductivity type source region, a trench penetrating the second conductivity type channel region from the surface of the first conductivity type source region and reaching the first conductivity type drain layer, and a gate insulating film provided in the trench A gate electrode layer; a source electrode provided in common contact with the surfaces of the first conductivity type source region and the second conductivity type channel region; and a drain electrode provided in contact with the first conductivity type drain layer; in trench type MOS semiconductor device consisting of a large expansion termination than the trench width provided in a circular shape in the planar direction of the semiconductor substrate at the end of the trench, the longitudinal direction of the trench to position the enlarged end portion of the adjacent trenches And staggered zigzag pattern to.
[0010]
[0011]
By doing so, the thinning of the gate oxide film at the upper corner of the terminal end of the trench is suppressed.
In addition, the position of the enlarged end portions provided at the end of the adjacent trenches so be shifted in a zigzag pattern in the longitudinal direction of the trenches, it is possible to increase the width of the enlarged end portion.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below based on examples with reference to the drawings.
[ Reference Example 1]
FIG. 1 is a plan view of the main part of a MOSFET according to a first reference example of the present invention. In addition to the main portion shown in the figure, there is a portion that mainly shares the breakdown voltage in the peripheral region, but it is omitted because it is not a portion related to the essence of the present invention.
[0013]
The difference from the conventional MOSFET of FIG. 4A is that the adjacent trench grooves are connected by a trench connecting portion 51 having a curvature so that there is no termination. For example, the width of the trench connecting portion 51 is 1.2 μm, the depth is 3 μm, the trench interval is 2.8 μm, and the radius of curvature of the outer periphery of the trench connecting portion 51 is 2.6 μm, like the trench 5. 17 is an edge of the field oxide film 2, and 16 is a step of the gate electrode. The thickness of the field oxide film 2 is about 450 nm, and the thickness of the gate electrode 4 on the semiconductor substrate is about 800 nm.
By doing so, it is possible to suppress the sharpening at the upper end corner of the trench 5 as in the prior art, and to prevent the gate oxide film 3 from being thinned at that portion.
[0014]
Also in the trench MOSFET actually fabricated, when the thickness of the gate oxide film is 100 nm, the breakdown voltage of the gate oxide film is 90 V or more, which is about 30% higher than the conventional 70 V. In addition, it is only necessary to change the etching mask for forming the trench 5, and it is not necessary to add a special process as in the example of JP-A-7-249769.
[0015]
[ Reference Example 2]
FIG. 2 is a plan view of the main part of a MOSFET according to a second reference example of the present invention.
In this example, a circular enlarged terminal portion 52 wider than the trench 5 is provided at the terminal of the trench 5. For example, the width of the trench 5 is 1.2 μm, the interval between the trenches is 2.8 μm, and the diameter of the enlarged terminal portion 52 is 2.8 μm.
[0016]
When the width of the trench 5 is 1.2 μm, the radius of curvature of the corner portion is 0.6 μm at the maximum in the conventional trench, but in this reference example, the radius of curvature is more than doubled to 1.4 μm. By increasing the size, the sharpening of the upper end corner of the trench is suppressed, and the breakdown voltage of the gate oxide film 3 can be improved.
[0017]
Also in the actually manufactured trench MOSFET, when the thickness of the gate oxide film is 100 nm, the breakdown voltage of the gate oxide film is 84V or more, which is about 20% higher than the conventional 70V.
[0018]
The diameter of the enlarged terminal portion 52 can be up to a value close to the sum of the trench width and the trench interval.
Also in this case, it is only necessary to change the mask pattern for trench etching, and there is no need to increase the number of processes.
[0019]
[Example 1 ]
FIG. 3 is a plan view of the main part of the MOSFET according to the first embodiment of the present invention.
In this example, the end of the trench 5 is provided with a circular enlarged end portion 52 having a width wider than that of the trench 5 in the same manner as in Reference Example 2, but the position of the enlarged peripheral end portion 52 is staggered between adjacent trenches. It is different in that it is shifted in a shape. By doing in this way, the diameter of the expansion | extension termination | terminus part 52 is enlarged with 4.8 micrometers.
[0020]
In this case as well, by further increasing the radius of curvature at the end of the trench, it is possible to suppress the sharpening of the upper corner of the end and further improve the breakdown voltage of the gate oxide film.
In the actually manufactured trench MOSFET, the breakdown voltage of the gate oxide film was 90 V or more.
[0021]
When the position of the enlarged peripheral end portion 52 is shifted in a staggered manner, the diameter of the enlarged end portion 52 can be up to a value close to twice the sum of the trench width and the trench interval. Needless to say, the shape of the enlarged terminal portion is not limited to a circular shape, and may be an annular shape, an elliptical shape, an elliptical annular shape, or the like.
[0022]
In each of the embodiments, an example of a MOSFET is shown, but the present invention can also be applied to a trench type MOS semiconductor device such as an IGBT, an insulated gate thyristor, and an IPM that is an assembly thereof.
[0023]
【The invention's effect】
As described above, according to the present invention, an enlarged termination portion that is circular in the planar direction of the semiconductor substrate and wider than the trench width is provided at the end of the trench, and the position of the enlarged termination portion of the adjacent trench is shifted in the longitudinal direction of the trench. By staggered, it is possible to easily improve the breakdown voltage of the gate oxide film by avoiding the problem of the sharpness of the upper corner of the trench end and the thinning of the gate oxide film due to the conventional problem. Can do.
[0024]
The method for manufacturing a trench type MOS semiconductor device according to the present invention can be realized very easily by simply changing the etching mask for forming the trench without increasing the number of steps.
[Brief description of the drawings]
[1] The present invention plan view of the reference example plan view of a first MOSFET FIG. 2 is a plan view of the present invention of Example 2 MOSFET of the present invention; FIG Example 1 MOSFET 4 (a) is A plan view of a conventional MOSFET, (b) is a sectional view taken along line AA in (a), (c) is a sectional view taken along line BB in (a), and (d) is a trench termination portion. [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5 Trench 6a n + type drain layer 6b n type drift layer 7 p type channel region 8 n type source region 9 Source electrode 10 Drain electrode 11 Insulating film 13 Gate metal electrode 14 Upper corner portion of trench termination 16 Gate electrode step 17 Field oxide film edge 18 Corner portion of trench 51 Trench connection portion 52 Expansion termination portion

Claims (1)

第一導電型ドレイン層と、その第一導電型ドレイン層上に設けられた第二導電型チャネル領域と、第二導電型チャネル領域の表面層に形成された第一導電型ソース領域と、その第一導電型ソース領域の表面から第二導電型チャネル領域を貫通し第一導電型ドレイン層に達するトレンチと、トレンチ内にゲート絶縁膜を介して設けられたゲート電極層と、第一導電型ソース領域と第二導電型チャネル領域との表面に共通に接触して設けられたソース電極と、第一導電型ドレイン層に接触して設けられたドレイン電極とからなるトレンチ型ＭＯＳ半導体装置において、トレンチの終端に半導体基板の平面方向で円状でトレンチ幅より広い拡大終端部を設け、隣接するトレンチの拡大終端部の位置をトレンチの長手方向にずらした千鳥状としたことを特徴とするトレンチ型ＭＯＳ半導体装置。A first conductivity type drain layer; a second conductivity type channel region provided on the first conductivity type drain layer; a first conductivity type source region formed on a surface layer of the second conductivity type channel region; A trench extending from the surface of the first conductivity type source region to the first conductivity type drain layer through the second conductivity type channel region, a gate electrode layer provided in the trench via a gate insulating film, and a first conductivity type In a trench type MOS semiconductor device comprising a source electrode provided in common contact with the surfaces of a source region and a second conductivity type channel region, and a drain electrode provided in contact with a first conductivity type drain layer, wide expansion termination than the trench width provided in a circular shape in the planar direction of the semiconductor substrate at the end of the trench, it was adjacent staggered by shifting the position of the enlarged end portion of the trench in the longitudinal direction of the trench Trench type MOS semiconductor device according to claim.
JP00041599A 1999-01-05 1999-01-05 Trench type MOS semiconductor device Expired - Lifetime JP4048628B2 (en)

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JP4491875B2 (en) * 1999-12-13 2010-06-30 富士電機システムズ株式会社 Trench type MOS semiconductor device
JP4639431B2 (en) * 2000-05-24 2011-02-23 富士電機システムズ株式会社 Trench gate type semiconductor device
CN100468774C (en) * 2004-09-29 2009-03-11 松下电器产业株式会社 Semiconductor device
US20060163650A1 (en) * 2005-01-27 2006-07-27 Ling Ma Power semiconductor device with endless gate trenches
JP2007048769A (en) * 2005-08-05 2007-02-22 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US7943990B2 (en) 2005-08-17 2011-05-17 International Rectifier Corporation Power semiconductor device with interconnected gate trenches
JP5531436B2 (en) * 2008-12-01 2014-06-25 富士電機株式会社 Method for manufacturing silicon carbide semiconductor element
JP5338448B2 (en) * 2009-04-21 2013-11-13 富士電機株式会社 Semiconductor device
JP5126335B2 (en) * 2010-10-18 2013-01-23 富士電機株式会社 Trench gate type semiconductor device
JP6135181B2 (en) * 2013-02-26 2017-05-31 サンケン電気株式会社 Semiconductor device
JP2015195285A (en) * 2014-03-31 2015-11-05 サンケン電気株式会社 semiconductor device
JP2018074126A (en) 2016-11-04 2018-05-10 トヨタ自動車株式会社 Semiconductor device
JP6679703B2 (en) * 2018-12-11 2020-04-15 ローム株式会社 SiC semiconductor device
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