JP2007129259A - Insulated-gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the difficulty in increasing the withstand voltage of a semiconductor device, the withstand voltage being limited by the dielectric breakdown of an insulator layer 9, the dielectric breakdown being caused by an increase in the field intensity of the insulator layer 9 disposed under a trench-type insulated gate, the field intensity being increased by applying a high voltage between a drain and a source so as to form no channels when a drift layer 2 of n-conductivity type has a large concentration of carriers in the semiconductor device having a trench-type insulated gate structure. <P>SOLUTION: The thickness of the bottom of the insulator layer 9 provided in the trench of the trench-type insulated gate semiconductor device is made considerably larger than that of the side of the insulator layer 9. The field intensity of the insulator layer on the bottom of the trench-type insulated gate is reduced, the insulator layer having a high field intensity in a semiconductor device having a conventional trench-type insulated gate structure. As a result, the withstand voltage of the semiconductor device is increased by about 15 to 30% as compared with the conventional semiconductor device, thereby improving the reliability of the insulator layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device used as a switching element.

Conventionally, MOSFETs and insulated gate bipolar transistors (hereinafter referred to as IGBTs) are known as vertical semiconductor devices for electric power having excellent high-speed switching characteristics and high input impedance and low input loss. In order to reduce the loss of both transistors, in order to reduce the resistance of a junction field effect transistor (hereinafter referred to as JFET) inherent in each semiconductor device, as shown in FIG. 11 and FIG. A semiconductor device having a trench-type insulated gate structure forming 14 is manufactured (see ISPSD '96 (The 8th International Symposium on Power Semiconductor Devices and ICs) Proceedings, pp. 119-122 (1996): Non-Patent Document 1). .
ISPSD'96 (The 8th International Symposium on Power Semiconductor Devices and ICs) Proceedings, pp.119-122 (1996)

11 and 12, when the carrier concentration of the n ⁻ conductivity type drift layer 2 as the semiconductor substrate having the first conductivity type (n) is high, The potential is made lower than the source potential (emitter potential in FIG. 12) so that a channel is not formed. In this case, when a positive high voltage is applied between the drain and the source (between the collector and the emitter in FIG. 12), the first conductivity type (partially or entirely provided on the semiconductor substrate having the first conductivity type). n) opposite to the second conductivity type having a (p), n ^- conductivity type n and p conductivity type body layer 4 of a semiconductor layer forming a junction between the drift layer 2 ^- conductivity type drift A depletion layer extends from the junction of layer 2. However, since the carrier concentration of the n ⁻ conductivity type drift layer 2 is large and the conductivity is high immediately below the gate 14, the resistance of the layer becomes small. As a result, the voltage sharing in the n ⁻ conductivity type drift layer 2 is reduced, and a high voltage is applied to the bottom of the insulator layer 9 formed on the inner surface of the recess 29. For this reason, the bottom electric field strength in the insulating layer 9 under the trench-type insulating gate is increased, and the withstand voltage is limited by the dielectric breakdown of the insulating layer 9, making it difficult to increase the withstand voltage of the device. Further, when the electric field strength in the insulator layer 9 is increased, the insulator layer 9 is deteriorated, and it is difficult to obtain high reliability.

  An object of the present invention is to provide an insulated gate semiconductor device having a high withstand voltage and high reliability by reducing the electric field strength under a trench type insulated gate layer.

  In the present invention, in order to solve the above-described problem, a first semiconductor region of a second conductivity type formed in a semiconductor substrate, ie, an electric field relaxation, is formed below a trench type insulated gate of a trench type insulated gate semiconductor device. The semiconductor region was provided. Thus, when a positive voltage is applied between the drain and source (or between the collector and emitter), for example, when the drift layer is the first conductivity type in FIGS. 1 to 10, the body layer of the second conductivity type is used. And a depletion layer spreads in the drift layer of the first conductivity type. On the other hand, in the lower part of the trench type insulated gate electrode, a depletion layer expands from the junction between the semiconductor region for electric field relaxation and the first conductivity type drift layer according to the drain-source (or collector-emitter) voltage, Most of the applied voltage is shared by the electric field relaxation semiconductor region and the first conductivity type drift layer. As a result, the voltage sharing at the bottom of the insulating layer of the gate is reduced, the electric field strength of the insulating layer is relaxed, and high breakdown voltage or high reliability of the semiconductor device can be achieved.

  The term “trench” used in the present invention is a concept including various shapes of holes and recesses in addition to grooves.

  In another embodiment of the present invention, the thickness of the insulating layer at the bottom of the trench-type insulating gate is significantly larger than the thickness of the insulating layer on the side surface. Thereby, high breakdown voltage or high reliability can be achieved. In this case, if a semiconductor region for reducing the electric field is provided, higher breakdown voltage or higher reliability can be achieved.

  In the insulated gate semiconductor device of the present invention, the first semiconductor region having the second conductivity type is formed at the bottom of the trench insulated gate, so that the conventional trench insulated gate semiconductor device has a high electric field. The electric field strength of the insulator layer at the bottom of the trench type insulated gate was relaxed. As a result, the breakdown voltage of the semiconductor device can be improved by about 15 to 30% compared to the conventional one. The relaxation of the electric field strength improves the reliability of the insulator layer.

  In the insulated gate semiconductor device of the present invention, the first semiconductor region having the second conductivity type is formed at the bottom of the trench type insulated gate, and the thickness of the insulator layer at the bottom of the trench type insulated gate is set to the thickness of the side surface. By increasing the thickness, the electric field strength of the insulator layer at the bottom of the trench type insulated gate, which was a high electric field in the conventional semiconductor device having the trench type insulated gate structure, was further relaxed. As a result, the breakdown voltage of the semiconductor device can be improved by about 45 to 65% compared to the conventional one. The relaxation of the electric field strength improves the reliability of the insulator layer.

  Further, the semiconductor substrate of the insulated gate semiconductor device of the present invention has a structure in which a layer having the same conductivity type and lower conductivity is provided on a substrate having higher conductivity, whereby the second electrode and the semiconductor are provided. The contact resistance with the substrate can be reduced. By forming this lower conductivity layer, the breakdown voltage of the semiconductor device can be increased.

  Furthermore, the conductivity of the second semiconductor region of the insulated gate semiconductor device of the present invention is determined by using the second conductivity type semiconductor layer having the second conductivity type in the semiconductor substrate and forming a junction with the semiconductor substrate. By making it higher than the conductivity of the layer forming the junction, the contact resistance between the first electrode and the second semiconductor region can be reduced, and the on-resistance of the semiconductor device can be reduced.

  Further, in an insulated gate semiconductor device in which a semiconductor layer of the second conductivity type is provided on a surface opposite to the surface having the junction of the semiconductor substrate, the first semiconductor region of the second conductivity type at the bottom of the trench gate. In the conventional semiconductor device having a trench type insulated gate structure, the electric field strength of the insulator layer at the bottom of the trench type insulated gate, which was a high electric field, was relaxed. As a result, the breakdown voltage of the semiconductor device can be improved by about 15 to 30% compared to the conventional one. The relaxation of the electric field strength improves the reliability of the insulator layer.

  Further, in an insulated gate semiconductor device in which a semiconductor layer of the second conductivity type is provided on a surface opposite to the surface having the junction of the semiconductor substrate, the first semiconductor region of the second conductivity type at the bottom of the trench gate. And the thickness of the insulator layer at the bottom of the trench-type insulated gate is made thicker than the thickness of the side surface portion. The electric field strength of the bottom insulator layer was relaxed. As a result, the breakdown voltage of the semiconductor device can be improved by about 45 to 65% compared to the conventional one. The relaxation of the electric field strength improves the reliability of the insulator layer.

  Furthermore, by selectively providing the third semiconductor region of the second conductivity type in the semiconductor substrate of the insulated gate semiconductor device of the present invention, it is possible to provide only the first semiconductor region of the second conductivity type. Furthermore, the electric field strength at the end on the insulator layer side at the bottom of the trench gate of the insulated gate semiconductor device could be reduced. As a result, the breakdown voltage of the semiconductor device can be improved by about 55 to 130% compared to the conventional one. The relaxation of the electric field strength further improves the reliability of the insulator layer.

  Further, in the horizontal semiconductor device in which the second electrode is provided in the same direction as the first electrode, the above-described high breakdown voltage or improved reliability can be achieved, and each semiconductor device has the second electrode in the same direction. Therefore, the degree of freedom of connection is increased and high integration is possible.

  Furthermore, by forming the first electric field relaxation semiconductor region of the second conductivity type also on the bottom portion of the trench and the side portion connected to the bottom portion, the electric field strength at the bottom side end portion of the trench type insulated gate can be further relaxed. And withstand voltage can be improved. In addition, the reliability of the insulating layer can be improved by reducing the electric field strength of the insulating layer.

  In addition, by making the thickness of the bottom of the insulator layer significantly thicker than the side surface, the electric field at the bottom of the insulator layer and the boundary between the bottom and the side surface can be greatly relaxed, and the breakdown voltage can be improved. Can do. In addition, the reliability of the insulator layer can be greatly improved by the relaxation of the electric field strength of the insulator layer.

  Further, by forming the first semiconductor region of the second conductivity type, the breakdown voltage can be further increased or the reliability can be improved.

  The insulated gate semiconductor device of the present invention has the following embodiments. That is, a second conductivity type semiconductor layer having a second conductivity type opposite to the first conductivity type and forming a junction with the semiconductor substrate is provided on a semiconductor substrate having the first conductivity type. Further, a recess penetrating through the semiconductor layer to a part of the semiconductor substrate is provided. A first semiconductor region of the second conductivity type is formed in the semiconductor substrate at the bottom of the recess. Furthermore, an insulating layer is formed on the inner surface of the recess, and at least a part of the gate insulated from the semiconductor substrate and the semiconductor layer of the second conductivity type by the insulating layer is provided in the recess. Furthermore, in the region around the gate surrounded by the insulating layer in the semiconductor layer, the first conductivity type from the surface of the semiconductor layer of the second conductivity type in the periphery of the gate to a predetermined depth. Forming a second semiconductor region. Further, a first electrode is provided conductively on the second conductive type semiconductor layer and the second semiconductor region, and a second electrode is provided on another portion of the semiconductor substrate.

  In the semiconductor substrate, a conductor layer of the same conductivity type and lower conductivity is provided on a semiconductor layer having higher conductivity.

  Further, the second semiconductor region has a higher conductivity than a portion of the semiconductor substrate that forms a junction with the semiconductor layer of the second conductivity type.

  Further, a second conductivity type layer is provided on the surface of the substrate opposite to the surface having the bonding.

  Further, a second semiconductor region of the third conductivity type is provided in the semiconductor substrate so as to be isolated from the recess.

  Furthermore, a layer of a second conductivity type is provided on the surface of the substrate opposite to the surface having the junction, and a second semiconductor region of the third conductivity type is isolated from the recess in the semiconductor substrate. Provided.

  Further, the second electrode is provided on the semiconductor substrate at a position separated from the first electrode by a predetermined distance.

  Furthermore, a first semiconductor region of the second conductivity type formed in the semiconductor substrate is provided on the bottom of the recess and the side connected to the bottom.

  Another insulated gate semiconductor device of the present invention has the following embodiment. That is, a second conductivity type semiconductor layer having a second conductivity type opposite to the first conductivity type and forming a junction with the semiconductor substrate is provided on a semiconductor substrate having the first conductivity type. Further, a recess penetrating through the semiconductor layer to a part of the semiconductor substrate is provided. An insulating layer having a bottom portion thicker than a side surface is formed on the inner surface of the recess, and at least a part of the gate insulated from the semiconductor substrate and the semiconductor layer of the second conductivity type by the insulating layer is formed in the recess. Provided. Furthermore, in the region around the gate surrounded by the insulating layer in the semiconductor layer, the first conductivity type from the surface of the semiconductor layer of the second conductivity type in the periphery of the gate to a predetermined depth. Forming a second semiconductor region. Further, a first electrode is provided conductively on the second conductive type semiconductor layer and the second semiconductor region, and a second electrode is provided on another portion of the semiconductor substrate.

  Further, a second conductivity type layer is provided on the surface of the substrate opposite to the surface having the bonding.

  Further, in the insulating layer formed on the inner surface of the recess, the thickness of the bottom insulating layer of the recess is about 5 to about 20 times the thickness of the side surface of the recess.

  Further, the thickness of the insulating layer formed at the bottom of the recess is about 0.5 to about 2 microns. In the present invention, the above-mentioned about 5, about 20, about 0.5, about 2, etc. should be understood to include an error range of about 20%.

(Example)
An embodiment of the present invention will be described with reference to FIGS.

<< Example 1 >>
FIG. 1 is a cross-sectional view of a unit segment of a withstand voltage 2500 V class n-channel SiC (silicon carbide) MOSFET that is Embodiment 1 of the present invention. In this embodiment, the segment width is 5 μm and the depth is 1 mm. Other structural specifications are as follows. The n ⁻ conductivity type drift layer 2 is provided on the n ⁺ conductivity type drain layer 3 and has a thickness of about 20 μm. The n ⁺ conductivity type drain layer 3 has a thickness of about 300 μm, the p conductivity type body layer 4 has a thickness of 4 μm, and the n ⁺ conductivity type source region 5 and the p conductivity type field relaxation semiconductor region 1 have junction depths of 0.5 μm each, the depth of the recess or trench 69 is 6 μm, the width of the trench is 3 μm, and the thickness of the insulating layer 9 such as SiO ₂ (silicon oxide) provided in the trench 69 is the bottom of the trench 69 and the side surface of the trench 69. 0.1 μm. In this embodiment, the trench type insulated gate electrode 14 has a long stripe shape in the depth direction of the paper. The planar shape of the trench may be, for example, a circular hole shape having a diameter of 3 μm or a square shape in addition to a long groove shape long in the depth direction of the paper as in this embodiment. For example, the trenches are arranged at equal intervals with a pitch of 5 μm. In the case of circular trenches, they may be arranged in a grid pattern or a zigzag pattern vertically and horizontally.

The specific example of the manufacturing method of a present Example is as follows. First, an n ^{+ type} SiC (silicon carbide) substrate 3 having a concentration of 10 ¹⁸ to 10 ²⁰ atm / cm ³ , for example, a concentration of 10 ¹⁹ atm / cm ³ , which functions as a drain region, is prepared. An SiC n ⁻ conductivity type drift layer 2 having a concentration of 10 ¹⁵ to 10 ¹⁶ atm / cm ³ , for example, about 5 × 10 ¹⁵ atm / cm ^{3, is} formed on one surface of the substrate 3 by vapor phase epitaxy or the like. . Next, a SiC p-conductivity type body layer 4 of about 10 ¹⁶ atm / cm ³ is formed on the drift layer 2 by vapor phase epitaxy or the like. Then, an n ⁺ conductivity type region 5 having a concentration of about 10 ¹⁸ atm / cm ^{3 is} selectively formed as a source layer by nitrogen ion implantation or the like (phosphorus or the like can be used instead of nitrogen).

Next, the substrate 3 as shown in FIG. 1, with a broad substrate made drift layer 2 and the body layer 4 is anisotropically etched bottom through the body layer 4 of the p conductivity type the n ^- conductivity type drift layer A trench (groove) 69 reaching 2 is formed. A p conductivity type field relaxation semiconductor region 1 having a depth of about 0.5 μm and about 10 ¹⁷ atm / cm ^{3 is formed} on the bottom by ion implantation of boron (or aluminum or the like). Subsequently, after forming a gate insulating film 9 of SiO _{2 on} the inner surface of the trench 69, polysilicon as a gate region containing phosphorus at a high concentration is deposited in the trench 69, and the trench 69 is buried to fill the gate region 14. create. One example of the dimensions of the trench 69 is a depth of 6 μm, a width of 3 μm, and a length of 1 mm. The dimensions shown here are examples, and other dimensions are used as necessary. The trench-type insulated gate electrode 14 is formed by leaving the polysilicon in the trench 69 and removing the remaining polysilicon at other locations (such as the substrate surface). Finally, the source electrode 11 is formed on the front surface and the drain electrode 10 is formed on the rear surface with aluminum (other nickel may be used) to complete an insulated gate semiconductor device (MOSFET). The on-resistance of this MOSFET was about 30 mΩ · cm ² .

This embodiment is an n-channel SiC MOSFET. In this device, the potential of the drain electrode 10 is higher than the potential of the source electrode 11, and the potential of the trench type insulated gate electrode 14, which is the gate electrode, is higher than the potential of the source electrode 11. A gate voltage is applied so that When this gate voltage exceeds the threshold voltage, an n conductivity type channel is formed on the surface of the p conductivity type body layer 4 on the side surface of the trench type insulated gate electrode 14. As a result, electrons flow from the n ⁺ conductivity type source region 5 through the channel into the n ⁻ conductivity type drift layer 2 and further into the n ⁺ conductivity type drain layer 3 to turn on the semiconductor device. Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 that is a gate electrode is equal to or lower than the potential of the source electrode 11, and the voltage is set so that the potential of the drain electrode 10 is higher than the potential of the source electrode 11. When applied, a depletion layer spreads on both sides of the junction 24 between the n ⁻ conductivity type drift layer 2 and the p conductivity type body layer 4. With this depletion layer, the electric field strength is relaxed, and withstand voltage withstanding the applied voltage is generated.

In this embodiment, in addition to the depletion layer extending on both sides of the junction 24, the junction between the p-conduction type field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 below the trench-type insulated gate electrode 14 is also used. A depletion layer spreads in each layer in accordance with the drain-source voltage, and a withstand voltage that can withstand the applied voltage is generated. Therefore, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 below the trench type insulated gate electrode 14. For this reason, the voltage sharing of the insulator layer 9 at the bottom of the gate is reduced, and the electric field strength of the insulator layer 9 is relaxed. Thereby, the electric field strength of the gate insulator layer 9 can be relaxed and the withstand voltage can be improved, and the reliability of the gate insulator layer 9 is improved.

In the prediction by calculation, in the case of the conventional trench type insulated gate MOSFET as shown in FIG. 11, the trench type insulated gate electrode 14 and the source electrode 11 are short-circuited, the source electrode 11 is set to 0V, and + 2000V is applied to the drain electrode 10. If the field intensity of the Si0 ₂ insulator layer 9 of the trench type insulated gate bottom becomes a value close to 6~10MV / cm is breakdown field strength of Si0 _2, the breakdown voltage of the semiconductor device is determined by the breakdown voltage of the SiO ₂ insulating film It was 2000V. On the other hand, in the case where the electric field relaxation semiconductor region 1 is formed below the trench type insulating gate 14 as in the MOSFET of the present embodiment, the electric field strength of the SiO ₂ insulator layer 9 at the end on the bottom side of the trench type insulating gate. Is reduced by 15 to 30% compared to the conventional one. As a result, the breakdown voltage of the semiconductor device was improved from 2300V to 2600V. In the case where the electric field relaxation semiconductor region 1 is not formed below the trench type insulating gate 14 as in the prior art, the voltage applied to the drain electrode 10 is applied to the bottom of the n ⁻ conductivity type drift layer 2 and the trench type insulating gate 14. The voltage sharing of the insulating layer 9 is increased by the insulating layer 9, and the electric field strength is increased accordingly. The breakdown voltage of the semiconductor device is determined by the breakdown voltage of the insulating layer. However, when the electric field relaxation semiconductor region 1 is formed below the trench type insulating gate 14 as in the present embodiment, the electric field relaxation semiconductor region 1, the n ⁻ conductivity type drift layer 2 and the trench type insulating gate bottom insulator layer 9 are used. Voltage is shared. In particular, most of the applied voltage between the drain and the source is shared near the junction between the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2. As a result, the voltage sharing of the insulator layer 9 at the bottom of the trench-type insulated gate 14 is reduced, and the electric field strength of the layer 9 is accordingly reduced. In the case of an element having a high breakdown voltage, the electric field strength of the insulator layer 9 at the bottom of the trench type insulating gate 14 is particularly high, and thus the effect of forming the electric field relaxation semiconductor region 1 below the trench type insulating gate 14 is remarkable. Become.

<< Example 2 >>
FIG. 2 is a cross-sectional view of an n-channel SiC IGBT segment according to the second embodiment of the present invention. The structure is such that a collector layer 6 of p conductivity type is formed instead of the drain layer 3 of n ⁺ conductivity type of the first embodiment. The structural specifications and manufacturing method of Example 2 differ only in that SiC-p ⁺ conductivity type substrate is used instead of the SiC-n ⁺ conductivity type substrate of Example 1, and the subsequent manufacturing process is the same as in Example 1. It is the same as the case of. The impurity concentration of the p ⁺ conductivity type substrate is 10 ¹⁸ to 10 ¹⁹ atm / cm ³ .

In the operation of the n-channel IGBT of the present embodiment, first, the potential of the collector electrode 12 is higher than the potential of the emitter electrode 13, and the potential of the trench type insulated gate electrode 14 as the gate electrode is higher than the potential of the emitter electrode 13. A gate voltage is applied to. When the gate voltage exceeds the threshold voltage, an n-conducting channel is formed on the surface of the p-conducting body layer 4 on the side surface of the trench-type insulated gate electrode 14, and the n ⁺ -conducting emitter region 7 Electrons flow into the n ⁻ conductivity type drift layer 2 through the channel. As a result, holes are injected from the p conductivity type collector layer 6 into the n ⁻ conductivity type drift layer 2 and turned on. At this time, since conductivity modulation occurs in the n ⁻ conductivity type drift layer 2, the on-resistance, which was very high in the MOSFET, is significantly reduced in the IGBT. In this example, the ON voltage was 1.5 V at a current of 200 A / cm ² , and the ON resistance was 7.5 mΩ · cm ² . Further, the gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 as the gate electrode is lower than the potential of the emitter electrode 13, and the voltage is set so that the potential of the collector electrode 12 is higher than the potential of the emitter electrode 13. When it is applied, a depletion layer spreads on both sides of the junction 24 of the n ⁻ conductivity type drift layer 2 and the p conductivity type body layer 4 to relax the electric field strength, resulting in a withstand voltage that can withstand the applied voltage. In the present embodiment, in addition to the voltage sharing by the depletion layer, the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 are also formed below the trench type insulated gate electrode 14 according to the collector-emitter voltage. A depletion layer spreads from the junction to each layer, resulting in a withstand voltage. Therefore, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 below the trench type insulated gate electrode 14. Therefore, the voltage sharing of the gate insulator layer 9 is reduced, and the electric field strength of the insulator layer 9 is relaxed. Thereby, the reliability of the gate insulator layer 9 is improved. In addition, the electric field strength of the gate insulator layer 9 is relaxed, and the breakdown voltage can be improved. Also in the case of the present embodiment, the electric field strength of the insulator layer 9 on the bottom side surface portion of the trench type insulated gate 14 is similar to that of the IGBT having the conventional structure in which the electric field relaxation semiconductor region 1 is not formed as in the case of the MOSFET described above. It is relaxed by about 15 to 30%. Therefore, also in this embodiment, the withstand voltage can be improved and the reliability of the gate insulator layer 9 is improved by reducing the electric field strength of the gate insulator layer 9. For example, according to the embodiment, the breakdown voltage can be improved from 2300V to 2600V.

<< Example 3 >>
FIG. 3 is a cross-sectional view of a unit segment of a withstand voltage 2500 V class n-channel SiC (silicon carbide) MOSFET that is Embodiment 3 of the present invention. In this embodiment, the segment width is 5 μm and the depth is 1 mm. Other structural specifications are as follows. The n ⁻ conductivity type drift layer 2 is provided on the n ⁺ conductivity type drain layer 3 and has a thickness of about 20 μm. The n ⁺ conductivity type drain layer 3 has a thickness of about 300 μm, the p conductivity type body layer 4 has a thickness of 4 μm, and the n ⁺ conductivity type source region 5 and the p conductivity type electric field relaxation semiconductor region 1 have junction depths of 0.5 μm each, the depth of the recess or trench 69 is 6 μm, the trench width is 3 μm, and the thickness of the insulating layer 9 such as SiO ₂ (silicon oxide) provided in the trench 69 is 0.5 μm at the bottom of the trench 69. It is 0.1 μm on the 69 side surfaces. In this embodiment, the trench type insulated gate electrode 14 has a long stripe shape in the depth direction of the paper. The planar shape of the trench may be, for example, a circular hole shape having a diameter of 3 μm or a square shape in addition to a long groove shape long in the paper depth direction as in this embodiment. For example, the trenches are arranged at equal intervals with a pitch of 5 μm. In the case of circular trenches, they may be arranged vertically or horizontally in a grid pattern or in a staggered pattern.

The specific example of the manufacturing method of a present Example is as follows. First, an n ^{+ type} SiC (silicon carbide) substrate 3 having a concentration of 10 ¹⁸ to 10 ²⁰ atm / cm ³ , for example, a concentration of 10 ¹⁹ atm / cm ³ , which functions as a drain region, is prepared. An SiC n ⁻ conductivity type drift layer 2 having a concentration of 10 ¹⁵ to 10 ¹⁶ atm / cm ³ , for example, about 5 × 10 ¹⁵ atm / cm ^{3, is} formed on one surface of the substrate 3 by vapor phase epitaxy or the like. . Next, a SiC p-conductivity type body layer 4 of about 10 ¹⁶ atm / cm ³ is formed on the drift layer 2 by vapor phase epitaxy or the like. Then, an n ⁺ conductivity type region 5 having a concentration of about 10 ¹⁸ atm / cm ^{3 is} selectively formed as a source layer by nitrogen ion implantation or the like (phosphorus or the like can be used instead of nitrogen).

Next, the substrate 3 as shown in FIG. 3, with a broad substrate made drift layer 2 and the body layer 4 is anisotropically etched bottom through the body layer 4 of the p conductivity type the n ^- conductivity type drift layer A trench (groove) 69 reaching 2 is formed. A p conductivity type field relaxation semiconductor region 1 having a depth of about 0.5 μm and about 10 ¹⁷ atm / cm ^{3 is formed} on the bottom by ion implantation of boron (or aluminum or the like). Subsequently, after forming a gate insulating film 9 of SiO _{2 on} the inner surface of the trench 69, polysilicon as a gate region containing phosphorus at a high concentration is deposited in the trench 69, and the trench 69 is buried to fill the gate region 14. create. One example of the dimensions of the trench 69 is a depth of 6 μm, a width of 3 μm, and a length of 1 mm. The dimensions shown here are examples, and other dimensions are used as necessary. The trench-type insulated gate electrode 14 is formed by leaving the polysilicon in the trench 69 and removing the remaining polysilicon at other locations (such as the substrate surface). Finally, the source electrode 11 is formed on the front surface and the drain electrode 10 is formed on the rear surface with aluminum (other nickel may be used) to complete an insulated gate semiconductor device (MOSFET). The on-resistance of this MOSFET was about 30 mΩ · cm ² .

This embodiment is an n-channel SiC MOSFET. In this device, the potential of the drain electrode 10 is higher than the potential of the source electrode 11, and the potential of the trench type insulated gate electrode 14, which is the gate electrode, is higher than the potential of the source electrode 11. A gate voltage is applied so that When this gate voltage exceeds the threshold voltage, an n conductivity type channel is formed on the surface of the p conductivity type body layer 4 on the side surface of the trench type insulated gate electrode 14. As a result, electrons flow from the n ⁺ conductivity type source region 5 through the channel into the n ⁻ conductivity type drift layer 2 and further into the n ⁺ conductivity type drain layer 3 to turn on the semiconductor device. Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 that is a gate electrode is equal to or lower than the potential of the source electrode 11, and the voltage is set so that the potential of the drain electrode 10 is higher than the potential of the source electrode 11. When applied, a depletion layer spreads on both sides of the junction 24 between the n ⁻ conductivity type drift layer 2 and the p conductivity type body layer 4. With this depletion layer, the electric field strength is relaxed, and withstand voltage withstanding the applied voltage is generated.

In this embodiment, in addition to the depletion layer extending on both sides of the junction 24, the junction between the p-conduction type field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 below the trench-type insulated gate electrode 14 is also used. A depletion layer spreads in each layer in accordance with the drain-source voltage, and a withstand voltage that can withstand the applied voltage is generated. Therefore, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 below the trench type insulated gate electrode 14. For this reason, the voltage sharing of the insulator layer 9 at the bottom of the gate is reduced, and the electric field strength of the insulator layer 9 is relaxed. Thereby, the electric field strength of the gate insulator layer 9 can be relaxed and the withstand voltage can be improved, and the reliability of the gate insulator layer 9 is improved.

In the prediction by calculation, in the case of the conventional trench type insulated gate MOSFET as shown in FIG. 11, the trench type insulated gate electrode 14 and the source electrode 11 are short-circuited, the source electrode 11 is set to 0V, and + 2000V is applied to the drain electrode 10. If the field intensity of the Si0 ₂ insulator layer 9 of the trench type insulated gate bottom has a value close to 6~10MV / cm is breakdown field strength of Si0 _2. On the other hand, as in the MOSFET of this embodiment, the electric field relaxation semiconductor region 1 is formed below the trench type insulating gate 14, and the thickness of the bottom portion of the insulator layer 9 is 0.5 μm thicker than the thickness of the side surface. in the example, the electric field strength of the Si0 ₂ insulator layer 9 of the trench type insulated gate bottom end is reduced from 45 to 65% as compared with the prior art. As a result, the breakdown voltage of the semiconductor device was improved from 2900V to 3250V. In the case where the electric field relaxation semiconductor region 1 is not formed below the trench type insulating gate 14 as in the prior art, the voltage applied to the drain electrode 10 is applied to the bottom of the n ⁻ conductivity type drift layer 2 and the trench type insulating gate 14. The voltage is shared by the insulating layer 9, and the voltage sharing of the insulating layer 9 increases, and the electric field strength increases accordingly. However, when the electric field relaxation semiconductor region 1 is formed below the trench type insulating gate 14 as in the present embodiment, the electric field relaxation semiconductor region 1, the n ⁻ conductivity type drift layer 2 and the trench type insulating gate bottom insulator layer 9 are used. Voltage is shared. In particular, most of the applied voltage between the drain and the source is shared near the junction between the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2. As a result, the voltage sharing of the insulator layer 9 at the bottom of the trench-type insulated gate 14 is reduced, and the electric field strength of the layer 9 is accordingly reduced. In the case of an element having a high breakdown voltage, the electric field strength of the insulator layer 9 at the bottom of the trench type insulating gate 14 is particularly high, and thus the effect of forming the electric field relaxation semiconductor region 1 below the trench type insulating gate 14 is remarkable. Become.

<< Example 4 >>
FIG. 4 is a cross-sectional view of an n-channel SiC IGBT segment according to the fourth embodiment of the present invention. The structure is such that a collector layer 6 of p conductivity type is formed instead of the drain layer 3 of n ⁺ conductivity type of the first embodiment. The structural specifications and manufacturing method of Example 2 differ only in that SiC-p ⁺ conductivity type substrate is used instead of the SiC-n ⁺ conductivity type substrate of Example 1, and the subsequent manufacturing process is the same as in Example 1. It is the same as the case of. The impurity concentration of the p ⁺ conductivity type substrate is 10 ¹⁸ to 10 ¹⁹ atm / cm ³ .

In the operation of the n-channel IGBT of the present embodiment, first, the potential of the collector electrode 12 is higher than the potential of the emitter electrode 13, and the potential of the trench type insulated gate electrode 14 as the gate electrode is higher than the potential of the emitter electrode 13. A gate voltage is applied to. When the gate voltage exceeds the threshold voltage, an n-conducting channel is formed on the surface of the p-conducting body layer 4 on the side surface of the trench-type insulated gate electrode 14, and the n ⁺ -conducting emitter region 7 Electrons flow into the n ⁻ conductivity type drift layer 2 through the channel. As a result, holes are injected from the p conductivity type collector layer 6 into the n ⁻ conductivity type drift layer 2 and turned on. At this time, since conductivity modulation occurs in the n ⁻ conductivity type drift layer 2, the on-resistance, which was very high in the MOSFET, is significantly reduced in the IGBT. In this example, the on-state voltage was 1.5 V at a current of 200 A / cm ² , and the on-resistance was 7.5 mΩ · cm ² . Further, the gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 as the gate electrode is lower than the potential of the emitter electrode 13, and the voltage is set so that the potential of the collector electrode 12 is higher than the potential of the emitter electrode 13. When applied, a depletion layer spreads on both sides of the junction 24 of the n ⁻ conductivity type drift layer 2 and the p conductivity type body layer 4 to relax the electric field strength, resulting in a voltage resistance that can withstand the applied voltage. In the present embodiment, in addition to the voltage sharing by the depletion layer, the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 are also formed below the trench type insulated gate electrode 14 according to the collector-emitter voltage. A depletion layer spreads from the junction to each layer, resulting in a withstand voltage. Therefore, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n ⁻ conductivity type drift layer 2 below the trench type insulated gate electrode 14. Therefore, the voltage sharing of the gate insulator layer 9 is reduced, and the electric field strength of the insulator layer 9 is relaxed. Thereby, the reliability of the gate insulator layer 9 is improved. In addition, the electric field strength of the gate insulator layer 9 is relaxed, and the breakdown voltage can be improved. Also in the case of the present embodiment, the electric field strength of the insulator layer 9 on the bottom side surface portion of the trench type insulated gate 14 is similar to that of the IGBT having the conventional structure in which the electric field relaxation semiconductor region 1 is not formed as in the case of the MOSFET described above. It is relaxed by about 45 to 65%. Therefore, also in this embodiment, the withstand voltage can be improved and the reliability of the gate insulator layer 9 is improved by reducing the electric field strength of the gate insulator layer 9. For example, according to the embodiment, the breakdown voltage can be improved from 2900V to 3250V.

<< Example 5 >>
FIG. 5 is a sectional view of a unit segment of the n-channel SiC MOSFET according to the fifth embodiment of the present invention. The fifth embodiment has a structure in which the second electric field relaxation semiconductor region 8 as the third semiconductor region of the second conductivity type (p) is provided in the n-conductivity type channel SiC MOSFET of the third embodiment. This electric field relaxation semiconductor region 8 is a region having a p conductivity type opposite to the n ⁻ conductivity type drift layer 2 having a thickness of 0.5 μm and a surface impurity concentration of about 10 ¹⁷ atm / cm ³ . The manufacturing method is the same as that of the MOSFET of Example 3 up to the formation of the n ⁻ conductivity type drift layer 2. The main difference from the manufacturing method of the third embodiment is that after the n ⁻ conductivity type drift layer 2 is formed, boron (or aluminum or the like) is selectively implanted by ion implantation or the like, and the second electric field relaxation semiconductor region 8. It is a point that forms. Since the subsequent manufacturing process is exactly the same as in the case of Example 3, the description is omitted.

In the MOSFET of Example 3, the electric field strength of the insulator layer 9 at the side end portion at the bottom of the trench-type insulated gate 14 was increased, and the withstand voltage was determined by the electric field strength of that portion. On the other hand, in the case where the second electric field relaxation semiconductor region 8 is formed as in the present embodiment, the depletion layer extends from the junction between the second electric field relaxation semiconductor region 8 and the n ⁻ conductivity type drift layer 2 to form a trench type. It is connected to a depletion layer extending from the junction between the electric field relaxation semiconductor region 1 below the insulating gate 14 and the n ⁻ conductivity type drift layer 2. The depletion layer extends in the n ⁻ conductivity type drift layer 2 to the drain electrode 10 side. As a result, the voltage applied between the drain and source electrodes is also shared by the above-described continuous depletion layer. For this reason, the voltage sharing of the insulator layer 9 is further reduced, and the electric field strength is further relaxed. In the present embodiment, the electric field strength of about 55% to 80% is relaxed compared to the conventional one. Therefore, the breakdown voltage of the semiconductor device of Example 5 is improved by about 55% or more compared to the conventional one. For example, the breakdown voltage can be improved from 3100V to about 3600V. The reliability of the insulator layer 9 can be further improved by the relaxation of the electric field strength. As an experimental example, a voltage application test of 3000 V was carried out, and a life that was twice as long as the conventional one was obtained.

<< Example 6 >>
FIG. 6 is a cross-sectional view of an n-channel SiC IGBT segment according to the sixth embodiment of the present invention. Example 6 has a structure in which a second electric field relaxation semiconductor region 8 is provided in an n-channel SiC IGBT. In this structure, a p ⁺ conductivity type collector layer 6 is formed instead of the n ⁺ conductivity type drain layer 3 of the third embodiment. In the structural specifications and manufacturing method of Example 6, the SiC-p conductivity type substrate is used instead of the SiC-n conductivity type substrate of Example 5, the drain layer is slightly reduced in concentration, and the thickness of the insulator layer 9 is increased. We are trying to improve the sheath quality. Other manufacturing processes are the same as those in the third embodiment. The impurity concentration of the p ⁺ conductivity type substrate is 10 ¹⁸ to 10 ¹⁹ atm / cm ³ . In the case of this embodiment, similarly to the case of the embodiment 5, there is an effect by forming the second electric field relaxation semiconductor region 8, and the electric field strength of the insulator layer 9 is relaxed. In the present embodiment, the electric field strength of about 65% to 130% is relaxed compared to the conventional one. Therefore, the breakdown voltage can be improved by about 25% or more in this semiconductor device, and the breakdown voltage can be improved from 3300V to about 4600V. The reliability of the insulator layer 9 can be improved by the relaxation of the electric field strength.

<< Example 7 >>
FIG. 7 is a cross-sectional view of a unit segment of an n-channel SiC MOSFET according to Example 7 of the present invention. In the seventh embodiment, the drain electrode 19 is provided not on the surface of the drain layer 3 in the first to fourth embodiments but on the surface of the drift layer 2 on which the body layer 4 is provided. Such a structure is called a horizontal insulated gate semiconductor device. In the seventh embodiment, instead of the p conductivity type body layer 4 provided in each of the above embodiments, for example, a striped p conductivity type body region 40 having a certain region is provided. An n ⁺ conductivity type drain region 33 is provided on the drift layer 2 at a certain distance from the body region 40. A drain electrode 19 is provided on the drain region 33.

  The drain electrode 19 is desirably provided in parallel with the insulated gate electrode 14 at a predetermined distance from the insulated gate electrode 14. Between the drain electrode 19 and the body region 40, one or more p-conduction type termination regions 15 are provided substantially in parallel with the body region 40. The termination region 15 is for relaxing the electric field concentration at the end of the body region 40. The structure other than the above points is the same as that of FIG.

  In the horizontal insulated gate semiconductor device, since the source terminal and the drain terminal are provided in the same direction, wiring work when incorporated in a hybrid IC or the like is simplified. Further, since the drain electrode 19 is provided in each semiconductor device, the degree of freedom of connection is increased.

  The configuration of the drain region and the drain electrode 19 shown in the seventh embodiment can be similarly applied to the configuration of the fifth embodiment shown in FIG.

Further, in the second embodiment of FIG. 2, the fourth embodiment of FIG. 4 and the sixth embodiment of FIG. 6, a p ⁺ conductivity type collector region corresponding to the collector layer 6 is provided on the surface of the body layer 4, and the collector region By providing the collector electrode, the configuration of FIG. 7 can be similarly applied to the apparatuses of Examples 2, 4, and 6.

<< Example 8 >>
FIG. 8 is a cross-sectional view of a segment of an n-channel SiC MOSFET according to Example 8 of the present invention. The structure of the eighth embodiment is substantially the same as that of the third embodiment, but differs from the third embodiment in the cross-sectional shape of the electric field relaxation semiconductor region and the manufacturing process. In the eighth embodiment, after forming the trench 69, when the electric field relaxation semiconductor region 1A is formed, the ion implantation amount of boron or the like is made larger than that in the third embodiment. Thereby, the diffusion of boron in the lateral direction in the n ⁻ conductivity type drift layer 2 proceeds more significantly at both ends of the bottom of the trench, and the electric field relaxation semiconductor region 1A is approximately the same as the depth direction as shown in FIG. It becomes the shape which swelled up to both sides. As a result, the electric field strength of the insulator layer 9 at the bottom side end of the trench type insulated gate 14 is further relaxed, and a higher breakdown voltage can be realized. The reason is that the voltage is shared in a wide and wide region of the electric field relaxation semiconductor region 1A. For example, the breakdown voltage of Example 8 shown in FIG. 8 increased from 3200 V to 3500 V compared to the breakdown voltage of 2900 to 3250 V of the semiconductor device of Example 3, and the reliability was further improved. On the other hand, in the case of the structure of FIG. 8, the on-resistance is slightly increased, but is practically not a problem. In addition, the electric field relaxation semiconductor region 1 </ b> A having a shape that swells on both sides of the present embodiment can be similarly applied to the first to seventh embodiments.

  The configurations of the drain region and the drain electrode 19 shown in the seventh embodiment can be similarly applied to the configuration of the eighth embodiment shown in FIG.

<< Example 9 >>
FIG. 9 is a cross-sectional view of a unit segment of a withstand voltage 2500 V class n-channel SiC (silicon carbide) MOSFET that is Embodiment 9 of the present invention. This embodiment attempts to improve the voltage sharing by making the trench bottom about 5 to about 20 times larger than the thickness of the insulating layer 9 on the side of the trench 69. In this embodiment, the segment width is 5 μm and the depth is 1 mm. Other structural specifications are as follows. The n ⁻ conductivity type drift layer 2 is provided on the n ⁺ conductivity type drain layer 3 and has a thickness of about 20 μm. The n ⁺ conductivity type drain layer 3 has a thickness of about 300 μm, the p conductivity type body layer 4 has a thickness of 4 μm, the n ⁺ conductivity type source region 5 has a junction depth of 0.5 μm, and the depth of the recess or trench 69. The thickness is 6 μm, the trench width is 3 μm, and the thickness of the insulating layer 9 such as SiO ₂ (silicon oxide) provided in the trench 69 is 1 μm at the bottom of the trench 69 and 0.1 μm at the side of the trench 69. In this embodiment, the trench type insulated gate electrode 14 has a long stripe shape in the depth direction of the paper. The planar shape of the trench may be, for example, a circular hole shape having a diameter of 3 μm or a square shape in addition to a long groove shape long in the depth direction of the paper as in this embodiment. For example, the trenches are arranged at equal intervals with a pitch of 5 μm. In the case of circular trenches, they may be arranged in a grid pattern or a zigzag pattern vertically and horizontally.

The specific example of the manufacturing method of a present Example is as follows. First, an n ^{+ type} SiC (silicon carbide) substrate 3 having a concentration of 10 ¹⁸ to 10 ²⁰ atm / cm ³ , for example, a concentration of 10 ¹⁹ atm / cm ³ , which functions as a drain region, is prepared. An SiC n ⁻ conductivity type drift layer 2 having a concentration of 10 ¹⁵ to 10 ¹⁶ atm / cm ³ , for example, about 5 × 10 ¹⁵ atm / cm ^{3, is} formed on one surface of the substrate 3 by vapor phase epitaxy or the like. . Next, a SiC p-conductivity type body layer 4 of about 10 ¹⁶ atm / cm ³ is formed on the drift layer 2 by vapor phase epitaxy or the like. Then, an n ⁺ conductivity type region 5 having a concentration of about 10 ¹⁸ atm / cm ^{3 is} selectively formed as a source layer by nitrogen ion implantation or the like (phosphorus or the like can be used instead of nitrogen).

Next, the substrate 3 as shown in FIG. 9, the broad substrate made drift layer 2 and the body layer 4 is anisotropically etched bottom through the body layer 4 of the p conductivity type the n ^- conductivity type drift layer A trench (groove) 69 reaching 2 is formed. Subsequently, a gate insulating film 9 of SiO ₂ is formed on the inner surface of the trench 69, further selectively increasing the thickness of the SiO ₂ gate insulating film 9 at the bottom of the trench by vapor phase deposition, and approximately 1 [mu] m. Then, polysilicon as a gate region containing phosphorus in a high concentration is deposited in the trench 69, and the trench 69 is buried to form the gate region. One example of the dimensions of the trench 69 is a depth of 6 μm, a width of 3 μm, and a length of 1 mm. The dimensions shown here are examples, and other dimensions are used as necessary. The trench-type insulated gate electrode 14 is formed by leaving the polysilicon in the trench 69 and removing the remaining polysilicon at other locations (such as the substrate surface). Finally, the source electrode 11 is formed on the front surface and the drain electrode 10 is formed on the rear surface with aluminum (other nickel may be used) to complete an insulated gate semiconductor device (MOSFET). The on-resistance of this MOSFET was about 30 mΩ · cm ² .

This embodiment is an n-channel SiC MOSFET. In this device, the potential of the drain electrode 10 is higher than the potential of the source electrode 11, and the potential of the trench type insulated gate electrode 14, which is the gate electrode, is higher than the potential of the source electrode 11. A gate voltage is applied so that When this gate voltage exceeds the threshold voltage, an n conductivity type channel is formed on the surface of the p conductivity type body layer 4 on the side surface of the trench type insulated gate electrode 14. As a result, electrons flow from the n ⁺ conductivity type source region 5 through the channel into the n ⁻ conductivity type drift layer 2 and further into the n ⁺ conductivity type drain layer 3 to turn on the semiconductor device. Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 that is a gate electrode is equal to or lower than the potential of the source electrode 11, and the voltage is set so that the potential of the drain electrode 10 is higher than the potential of the source electrode 11. When applied, a depletion layer spreads on both sides of the junction 24 between the n ⁻ conductivity type drift layer 2 and the p conductivity type body layer 4. With this depletion layer, the electric field strength is relaxed, and withstand voltage withstanding the applied voltage is generated.

  In this embodiment, the electric field at the bottom of the insulator layer 9 and the bottom side edge is alleviated by increasing the thickness of the bottom of the trench of the insulator layer 9 to 1 μm, which is several times to 10 times thicker than the thickness of the side surface of the trench. Is done. Thereby, the withstand voltage can be improved. Alternatively, the reliability of the gate insulator layer 9 can be improved.

In the prediction by calculation, in the case of the conventional trench type insulated gate MOSFET as shown in FIG. 11, the trench type insulated gate electrode 14 and the source electrode 11 are short-circuited, the source electrode 11 is set to 0V, and + 2000V is applied to the drain electrode 10. If the field intensity of the Si0 ₂ insulator layer 9 of the trench type insulated gate bottom has a value of greater than 6~10MV / cm is breakdown field strength of Si0 _2. In contrast, those that the thickness of the insulator layer 9 as in the MOSFET of this embodiment was 1 [mu] m, the electric field strength of the Si0 ₂ insulator layer 9 of the trench type insulated gate bottom end, with the conventional Compared to 90% reduction. The reliability of the insulating layer is greatly reduced when the electric field strength is close to the breakdown electric field strength. In the present example, the electric field strength of the insulator layer 9 was significantly reduced, so that the reliability was greatly improved. As a result, the breakdown voltage of the semiconductor device was improved from 2900V to 3250V. Further, by increasing the thickness of the n ⁻ drift layer, it is possible to further increase the breakdown voltage. The voltage applied to the drain electrode 10 is shared by the n ⁻ conductivity type drift layer 2 and the insulating layer 9 at the bottom of the trench type insulating gate 14, and the voltage sharing of the insulating layer 9 is increased, and the electric field strength is accordingly increased. It was getting bigger. However, when the thickness of the insulator at the bottom of the trench type insulated gate 14 is about 1 μm or more as in this embodiment, the voltage is shared by the n ⁻ conductivity type drift layer 2 and the trench type insulated gate bottom insulator layer 9. In particular, most of the applied drain-source voltage is shared at the bottom of the insulator layer 9. However, as the thickness of the insulator layer 9 is increased, the electric field strength of the layer 9 is also reduced. In the case of an element having a high breakdown voltage, the electric field strength of the insulator layer 9 at the bottom of the trench-type insulated gate 14 is particularly high, so that the effect of increasing the thickness of the bottom of the insulator layer 9 becomes significant.

  In the ninth embodiment, the same effect as in the fifth embodiment can be obtained by providing a portion corresponding to the second electric field relaxation semiconductor region 8 in the fifth embodiment.

  In the ninth embodiment, when the drain electrode 19 is provided in parallel to the insulated gate electrode 14 at a predetermined distance from the insulated gate electrode 14 as in the seventh embodiment, the same effect as in the seventh embodiment can be obtained. .

<< Example 10 >>
FIG. 10 is a cross-sectional view of an n-channel SiC IGBT segment according to the tenth embodiment of the present invention. The structure is such that a p conductivity type collector layer 6 is formed instead of the n ⁺ conductivity type drain layer 3 of the ninth embodiment. The structural specifications and manufacturing method of Example 10 differ only in that SiC-p ⁺ conductivity type substrate is used instead of the SiC-n ⁺ conductivity type substrate of Example 9, and the subsequent manufacturing process is the same as in Example 9. It is the same as the case of. The impurity concentration of the p ⁺ conductivity type substrate is 10 ¹⁸ to 10 ¹⁹ atm / cm ³ .

In the operation of the n-channel IGBT of the present embodiment, first, the potential of the collector electrode 12 is higher than the potential of the emitter electrode 13, and the potential of the trench type insulated gate electrode 14 as the gate electrode is higher than the potential of the emitter electrode 13. A gate voltage is applied to. When the gate voltage exceeds the threshold voltage, an n-conducting channel is formed on the surface of the p-conducting body layer 4 on the side surface of the trench-type insulated gate electrode 14, and the n ⁺ -conducting emitter region 7 Electrons flow into the n ⁻ conductivity type drift layer 2 through the channel. As a result, holes are injected from the p conductivity type collector layer 6 into the n ⁻ conductivity type drift layer 2 and turned on. At this time, since conductivity modulation occurs in the n ⁻ conductivity type drift layer 2, the on-resistance, which was very high in the MOSFET, is significantly reduced in the IGBT. In this example, the ON voltage was 1.5 V at a current of 200 A / cm ² , and the ON resistance was 7.5 mΩ · cm ² . Further, the gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 as the gate electrode is lower than the potential of the emitter electrode 13, and the voltage is set so that the potential of the collector electrode 12 is higher than the potential of the emitter electrode 13. When it is applied, a depletion layer spreads on both sides of the junction 24 of the n ⁻ conductivity type drift layer 2 and the p conductivity type body layer 4 to relax the electric field strength, resulting in a withstand voltage that can withstand the applied voltage.

  In the present embodiment, most of the applied voltage is shared by the bottom of the insulator layer 9 below the trench-type insulated gate electrode 14, but by increasing the thickness of the bottom of the insulator layer 9, the bottom and bottom side edges The electric field strength of the part is relaxed. Thereby, the reliability of the gate insulator layer 9 is greatly improved. In addition, since the electric field strength of the gate insulator layer 9 is relaxed, the breakdown voltage can be improved. Also in the case of the present embodiment, as in the case of the MOSFET described above, the electric field strength of the insulator layer 9 on the bottom side surface portion of the trench-type insulated gate 14 is the same as that of an IGBT having a conventional structure in which the insulator layer 9 is not significantly thickened. Compared to about 90%. Therefore, also in this embodiment, the withstand voltage can be improved by reducing the electric field strength of the gate insulator layer 9, and the reliability of the gate insulator layer 9 is greatly improved. For example, according to the embodiment, the breakdown voltage can be improved from 2900V to 3250V.

  In the tenth embodiment, the same effect as in the sixth embodiment can be obtained by providing one corresponding to the second electric field relaxation semiconductor region 8 in the sixth embodiment.

  In the tenth embodiment, as in the seventh embodiment, when the collector electrode 12 is provided in parallel to the insulated gate electrode 14 at a predetermined distance from the insulated gate electrode 14, the same effect as in the seventh embodiment can be obtained. .

The present invention has been described above with respect to the first to tenth embodiments. However, the present invention is not limited to these embodiments, and a trench type MOS thyristor, a trench type static induction transistor, a thyristor, and an IEGT (Injection Enhanced Insulated Gate). Bipolar Transistor) can be applied to various modifications and applications. The insulator layer 9 may be other insulators such as Ta ₂ O ₅ (tantalum oxide), Si ₃ N ₄ (silicon nitride), and AlN (aluminum nitride) in addition to SiO ₂ . Furthermore, in the embodiment of the present invention, the gate has a structure in which the trench is embedded, but this is not always necessary, and the gate may be formed as a thin film on a part of the inner wall of the trench 69 via the SiO ₂ insulator layer 9. It doesn't matter.

Sectional drawing of the insulated gate semiconductor device of Example 1 of this invention Sectional drawing of the insulated gate semiconductor device of Example 2 of this invention Sectional drawing of the insulated gate semiconductor device of Example 3 of this invention Sectional drawing of the insulated gate semiconductor device of Example 4 of this invention Sectional drawing of the insulated gate semiconductor device of Example 5 of this invention Sectional drawing of the insulated gate semiconductor device of Example 6 of this invention Sectional drawing of the insulated gate semiconductor device of Example 7 of this invention Sectional drawing of the insulated gate semiconductor device of Example 8 of this invention Sectional drawing of the insulated gate semiconductor device of Example 9 of this invention Sectional drawing of the insulated gate semiconductor device of Example 10 of this invention Sectional view of a conventional MOSFET insulated gate semiconductor device Sectional view of conventional IGBT insulated gate semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1A: Electric field relaxation semiconductor region 2: n ^- conductivity type drift layer 3: n ⁺ conductivity type drain layer 4: p conductivity type body layer 5: n ⁺ conductivity type source region 6: p conductivity type collector Layer 7: n ⁺ conductivity type emitter region 8: Second electric field relaxation semiconductor region 9: Trench type insulated gate insulator layer 10: Drain electrode 11: Source electrode 12: Collector electrode 13: Emitter electrode 14: Trench type insulated gate electrode 15: termination region 19: drain electrode 24: n ^- conductivity type of the drift layer and the p conductivity type body layer and the joining portion 33: drain region 40: the body region 69: trench

Claims (4)

A semiconductor substrate having a first conductivity type;
A semiconductor layer of a second conductivity type provided on the semiconductor substrate and having a second conductivity type opposite to the first conductivity type and forming a junction with the semiconductor substrate;
At least one recess extending through the semiconductor layer to a part of the semiconductor substrate;
An insulating layer formed on the inner surface of the recess and having a thickness larger than a side surface of the recess at the bottom of the recess;
A gate that is insulated from the substrate and the semiconductor layer by the insulating layer and at least partially provided in the recess;
A first conductivity type second semiconductor formed from the surface of the second conductivity type semiconductor layer to a predetermined depth in a region around the gate surrounded by the insulating layer in the semiconductor layer. region,
A first electrode conductively provided on the second conductive type semiconductor layer and the second semiconductor region; and a second electrode provided on another portion of the semiconductor substrate;
An insulated gate semiconductor device comprising:   2. The insulated gate semiconductor device according to claim 1, wherein a layer of a second conductivity type is provided on a surface of the substrate opposite to the surface having the junction.   The insulated gate semiconductor device according to claim 1 or 2, wherein the insulating layer formed on the inner surface of the recess has a thickness of the insulating layer at the bottom of the recess that is about 5 to about 20 times the thickness of the side surface of the recess. .   3. The insulated gate semiconductor device according to claim 1, wherein the thickness of the insulating layer formed at the bottom of the recess is about 0.5 to about 2 microns.

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