FR2282722A1 - Procede pour profiler des plaquettes semi-conductrices et dispositif ainsi obtenu - Google Patents

Procede pour profiler des plaquettes semi-conductrices et dispositif ainsi obtenu

Info

Publication number
FR2282722A1
FR2282722A1 FR7525662A FR7525662A FR2282722A1 FR 2282722 A1 FR2282722 A1 FR 2282722A1 FR 7525662 A FR7525662 A FR 7525662A FR 7525662 A FR7525662 A FR 7525662A FR 2282722 A1 FR2282722 A1 FR 2282722A1
Authority
FR
France
Prior art keywords
profiling
semiconductor plates
semiconductor
plates
profiling semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7525662A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of FR2282722A1 publication Critical patent/FR2282722A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)
FR7525662A 1974-08-21 1975-08-19 Procede pour profiler des plaquettes semi-conductrices et dispositif ainsi obtenu Withdrawn FR2282722A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49928874A 1974-08-21 1974-08-21

Publications (1)

Publication Number Publication Date
FR2282722A1 true FR2282722A1 (fr) 1976-03-19

Family

ID=23984661

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7525662A Withdrawn FR2282722A1 (fr) 1974-08-21 1975-08-19 Procede pour profiler des plaquettes semi-conductrices et dispositif ainsi obtenu

Country Status (7)

Country Link
JP (1) JPS5146076A (fr)
BE (1) BE832633A (fr)
CA (1) CA1038969A (fr)
DE (1) DE2536108A1 (fr)
FR (1) FR2282722A1 (fr)
GB (1) GB1471116A (fr)
IT (1) IT1040004B (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2356739A1 (fr) * 1976-07-02 1978-01-27 Philips Nv Procede de decapage a l'aide d'un plasma et dispositif obtenu
FR2410366A1 (fr) * 1977-11-29 1979-06-22 Radiotechnique Compelec Transistor de type mesa et procede de realisation de ce transistor
EP0164645A2 (fr) * 1984-06-14 1985-12-18 Asea Brown Boveri Aktiengesellschaft Dispositif semi-conducteur en silicium avec un contour de bord formé par attaque chimique et procédé pour fabriquer ce dispositif
EP0423722A2 (fr) * 1989-10-16 1991-04-24 Kabushiki Kaisha Toshiba Procédé pour la fabrication d'une structure d'isolation diélectrique complète pour circuit intégré à isolant

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895553A (ja) * 1981-12-01 1983-06-07 Nippon Shokubai Kagaku Kogyo Co Ltd 耐熱衝撃性の改良されたハニカム触媒の製造方法
GB2176338A (en) * 1985-06-06 1986-12-17 Marconi Electronic Devices Edge contouring in a semiconductor device
JPH0777240B2 (ja) * 1989-01-20 1995-08-16 富士通株式会社 半導体装置の製造方法
DE19536438A1 (de) * 1995-09-29 1997-04-03 Siemens Ag Halbleiterbauelement und Herstellverfahren

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2356739A1 (fr) * 1976-07-02 1978-01-27 Philips Nv Procede de decapage a l'aide d'un plasma et dispositif obtenu
FR2410366A1 (fr) * 1977-11-29 1979-06-22 Radiotechnique Compelec Transistor de type mesa et procede de realisation de ce transistor
EP0164645A2 (fr) * 1984-06-14 1985-12-18 Asea Brown Boveri Aktiengesellschaft Dispositif semi-conducteur en silicium avec un contour de bord formé par attaque chimique et procédé pour fabriquer ce dispositif
EP0164645A3 (fr) * 1984-06-14 1987-09-30 Asea Brown Boveri Aktiengesellschaft Dispositif semi-conducteur en silicium avec un contour de bord formé par attaque chimique et procédé pour fabriquer ce dispositif
EP0423722A2 (fr) * 1989-10-16 1991-04-24 Kabushiki Kaisha Toshiba Procédé pour la fabrication d'une structure d'isolation diélectrique complète pour circuit intégré à isolant
EP0423722A3 (en) * 1989-10-16 1993-01-13 Kabushiki Kaisha Toshiba Method of making complete dielectric isolation structure in semiconductor integrated circuit

Also Published As

Publication number Publication date
GB1471116A (en) 1977-04-21
JPS5227033B2 (fr) 1977-07-18
IT1040004B (it) 1979-12-20
BE832633A (fr) 1975-12-16
JPS5146076A (ja) 1976-04-20
CA1038969A (fr) 1978-09-19
DE2536108A1 (de) 1976-03-11

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Legal Events

Date Code Title Description
ST Notification of lapse