FR2356739A1 - Procede de decapage a l'aide d'un plasma et dispositif obtenu - Google Patents

Procede de decapage a l'aide d'un plasma et dispositif obtenu

Info

Publication number
FR2356739A1
FR2356739A1 FR7720247A FR7720247A FR2356739A1 FR 2356739 A1 FR2356739 A1 FR 2356739A1 FR 7720247 A FR7720247 A FR 7720247A FR 7720247 A FR7720247 A FR 7720247A FR 2356739 A1 FR2356739 A1 FR 2356739A1
Authority
FR
France
Prior art keywords
plasma
stripping process
device obtained
photosensitive varnish
pickled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7720247A
Other languages
English (en)
Other versions
FR2356739B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2356739A1 publication Critical patent/FR2356739A1/fr
Application granted granted Critical
Publication of FR2356739B1 publication Critical patent/FR2356739B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/127—Structure or manufacture of heads, e.g. inductive
    • G11B5/31—Structure or manufacture of heads, e.g. inductive using thin films
    • G11B5/3163—Fabrication methods or processes specially adapted for a particular head structure, e.g. using base layers for electroplating, using functional layers for masking, using energy or particle beams for shaping the structure or modifying the properties of the basic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

L'invention concerne un procédé pour le décapage à plasma d'un corps, selon lequel une surface du corps est recouverte d'un masque en vernis photosensible. Conformément à l'invention, le masque en vernis photosensible appliqué dépasse les dimensions requises de la configuration décapée à former puis, le procédé est effectué de façon que le masque en vernis photosensible soit plus rapidement décapé que le corps. Il se forme un profil de décapage présentant des bords inclinés. Application : réalisation de dispositifs semiconducteurs.
FR7720247A 1976-07-02 1977-07-01 Procede de decapage a l'aide d'un plasma et dispositif obtenu Granted FR2356739A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7607298A NL7607298A (nl) 1976-07-02 1976-07-02 Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze.

Publications (2)

Publication Number Publication Date
FR2356739A1 true FR2356739A1 (fr) 1978-01-27
FR2356739B1 FR2356739B1 (fr) 1982-06-18

Family

ID=19826508

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7720247A Granted FR2356739A1 (fr) 1976-07-02 1977-07-01 Procede de decapage a l'aide d'un plasma et dispositif obtenu

Country Status (9)

Country Link
US (1) US4293375A (fr)
JP (1) JPS6031100B2 (fr)
CA (1) CA1097434A (fr)
CH (1) CH630961A5 (fr)
DE (1) DE2727788C2 (fr)
FR (1) FR2356739A1 (fr)
GB (1) GB1571034A (fr)
IT (1) IT1081122B (fr)
NL (1) NL7607298A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0057738A2 (fr) * 1981-02-07 1982-08-18 Ibm Deutschland Gmbh Procédé pour la réalisation et le remplissage de trous dans une couche appliquée sur un substrat
EP0436387A2 (fr) * 1990-01-03 1991-07-10 Hewlett-Packard Company Gravure de trous de contacts dans un diélectrique bicouche utilisant une unique chambre d'attaque

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183780A (en) * 1978-08-21 1980-01-15 International Business Machines Corporation Photon enhanced reactive ion etching
EP0050973B1 (fr) * 1980-10-28 1986-01-22 Kabushiki Kaisha Toshiba Procédé de masquage pour dispositif semiconducteurs utilisant une couche de polymère
JPS5775429A (en) * 1980-10-28 1982-05-12 Toshiba Corp Manufacture of semiconductor device
JPS57170535A (en) * 1981-04-15 1982-10-20 Toshiba Corp Etching method for thin silicon film
DE3215410A1 (de) * 1982-04-24 1983-10-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen von oeffnungen mit hilfe einer maske in einer auf einer unterlage befindlichen schicht
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
US4522681A (en) * 1984-04-23 1985-06-11 General Electric Company Method for tapered dry etching
DE3903699A1 (de) * 1988-02-08 1989-08-17 Ricoh Kk Bildsensor
JPH0964366A (ja) * 1995-08-23 1997-03-07 Toshiba Corp 薄膜トランジスタ
JP2016219452A (ja) * 2015-05-14 2016-12-22 富士通株式会社 多層基板及び多層基板の製造方法
CN111725063B (zh) * 2020-06-19 2024-05-17 北京北方华创微电子装备有限公司 半导体衬底的刻蚀方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1570763A (fr) * 1967-05-29 1969-06-13
FR2132745A1 (fr) * 1971-04-08 1972-11-24 Philips Nv
FR2282722A1 (fr) * 1974-08-21 1976-03-19 Rca Corp Procede pour profiler des plaquettes semi-conductrices et dispositif ainsi obtenu

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3767490A (en) * 1971-06-29 1973-10-23 Ibm Process for etching organic coating layers
US3795557A (en) * 1972-05-12 1974-03-05 Lfe Corp Process and material for manufacturing semiconductor devices
NL7213625A (fr) * 1972-10-07 1974-04-09
US3880684A (en) * 1973-08-03 1975-04-29 Mitsubishi Electric Corp Process for preparing semiconductor
US3839111A (en) * 1973-08-20 1974-10-01 Rca Corp Method of etching silicon oxide to produce a tapered edge thereon
JPS51117136A (en) * 1975-04-09 1976-10-15 Tokyo Shibaura Electric Co Plasma etching process
US3986912A (en) * 1975-09-04 1976-10-19 International Business Machines Corporation Process for controlling the wall inclination of a plasma etched via hole

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1570763A (fr) * 1967-05-29 1969-06-13
FR2132745A1 (fr) * 1971-04-08 1972-11-24 Philips Nv
FR2282722A1 (fr) * 1974-08-21 1976-03-19 Rca Corp Procede pour profiler des plaquettes semi-conductrices et dispositif ainsi obtenu

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/67 *
EXBK/72 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0057738A2 (fr) * 1981-02-07 1982-08-18 Ibm Deutschland Gmbh Procédé pour la réalisation et le remplissage de trous dans une couche appliquée sur un substrat
EP0057738A3 (en) * 1981-02-07 1984-06-13 Ibm Deutschland Gmbh Process for the formation and the filling of holes in a layer applied to a substrate
EP0436387A2 (fr) * 1990-01-03 1991-07-10 Hewlett-Packard Company Gravure de trous de contacts dans un diélectrique bicouche utilisant une unique chambre d'attaque
EP0436387A3 (en) * 1990-01-03 1991-10-16 Hewlett-Packard Company Single chamber via etch through a dual-layer dielectric

Also Published As

Publication number Publication date
CA1097434A (fr) 1981-03-10
DE2727788A1 (de) 1978-01-05
CH630961A5 (de) 1982-07-15
IT1081122B (it) 1985-05-16
US4293375A (en) 1981-10-06
JPS6031100B2 (ja) 1985-07-20
GB1571034A (en) 1980-07-09
DE2727788C2 (de) 1982-08-19
NL7607298A (nl) 1978-01-04
JPS535974A (en) 1978-01-19
FR2356739B1 (fr) 1982-06-18

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