IT1081122B - Metodo di fabbricazione di un dispositivo,e dispositivo fabbricato con l'ausilio di tale metodo - Google Patents
Metodo di fabbricazione di un dispositivo,e dispositivo fabbricato con l'ausilio di tale metodoInfo
- Publication number
- IT1081122B IT1081122B IT25218/77A IT2521877A IT1081122B IT 1081122 B IT1081122 B IT 1081122B IT 25218/77 A IT25218/77 A IT 25218/77A IT 2521877 A IT2521877 A IT 2521877A IT 1081122 B IT1081122 B IT 1081122B
- Authority
- IT
- Italy
- Prior art keywords
- aid
- manufacturing
- manufactured
- device manufactured
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/127—Structure or manufacture of heads, e.g. inductive
- G11B5/31—Structure or manufacture of heads, e.g. inductive using thin films
- G11B5/3163—Fabrication methods or processes specially adapted for a particular head structure, e.g. using base layers for electroplating, using functional layers for masking, using energy or particle beams for shaping the structure or modifying the properties of the basic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
- H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7607298A NL7607298A (nl) | 1976-07-02 | 1976-07-02 | Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze. |
Publications (1)
Publication Number | Publication Date |
---|---|
IT1081122B true IT1081122B (it) | 1985-05-16 |
Family
ID=19826508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT25218/77A IT1081122B (it) | 1976-07-02 | 1977-06-29 | Metodo di fabbricazione di un dispositivo,e dispositivo fabbricato con l'ausilio di tale metodo |
Country Status (9)
Country | Link |
---|---|
US (1) | US4293375A (it) |
JP (1) | JPS6031100B2 (it) |
CA (1) | CA1097434A (it) |
CH (1) | CH630961A5 (it) |
DE (1) | DE2727788C2 (it) |
FR (1) | FR2356739A1 (it) |
GB (1) | GB1571034A (it) |
IT (1) | IT1081122B (it) |
NL (1) | NL7607298A (it) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4183780A (en) * | 1978-08-21 | 1980-01-15 | International Business Machines Corporation | Photon enhanced reactive ion etching |
JPS5775429A (en) * | 1980-10-28 | 1982-05-12 | Toshiba Corp | Manufacture of semiconductor device |
EP0050973B1 (en) * | 1980-10-28 | 1986-01-22 | Kabushiki Kaisha Toshiba | Masking process for semiconductor devices using a polymer film |
EP0057738B1 (de) * | 1981-02-07 | 1986-10-15 | Ibm Deutschland Gmbh | Verfahren zum Herstellen und Füllen von Löchern in einer auf einem Substrat aufliegenden Schicht |
JPS57170535A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Etching method for thin silicon film |
DE3215410A1 (de) * | 1982-04-24 | 1983-10-27 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zum herstellen von oeffnungen mit hilfe einer maske in einer auf einer unterlage befindlichen schicht |
US4461672A (en) * | 1982-11-18 | 1984-07-24 | Texas Instruments, Inc. | Process for etching tapered vias in silicon dioxide |
US4522681A (en) * | 1984-04-23 | 1985-06-11 | General Electric Company | Method for tapered dry etching |
DE3903699A1 (de) * | 1988-02-08 | 1989-08-17 | Ricoh Kk | Bildsensor |
US4978420A (en) * | 1990-01-03 | 1990-12-18 | Hewlett-Packard Company | Single chamber via etch through a dual-layer dielectric |
JPH0964366A (ja) * | 1995-08-23 | 1997-03-07 | Toshiba Corp | 薄膜トランジスタ |
JP2016219452A (ja) * | 2015-05-14 | 2016-12-22 | 富士通株式会社 | 多層基板及び多層基板の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3483108A (en) * | 1967-05-29 | 1969-12-09 | Gen Electric | Method of chemically etching a non-conductive material using an electrolytically controlled mask |
DE2117199C3 (de) * | 1971-04-08 | 1974-08-22 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Verfahren zur Herstellung geätzter Muster in dünnen Schichten mit definierten Kantenprofilen |
US3767490A (en) * | 1971-06-29 | 1973-10-23 | Ibm | Process for etching organic coating layers |
US3795557A (en) * | 1972-05-12 | 1974-03-05 | Lfe Corp | Process and material for manufacturing semiconductor devices |
NL7213625A (it) * | 1972-10-07 | 1974-04-09 | ||
US3880684A (en) * | 1973-08-03 | 1975-04-29 | Mitsubishi Electric Corp | Process for preparing semiconductor |
US3839111A (en) * | 1973-08-20 | 1974-10-01 | Rca Corp | Method of etching silicon oxide to produce a tapered edge thereon |
IT1040004B (it) * | 1974-08-21 | 1979-12-20 | Rca Corp | Metodo per la creazione del con torno marginale di una lastrina di materiale semiconduttore |
JPS51117136A (en) * | 1975-04-09 | 1976-10-15 | Tokyo Shibaura Electric Co | Plasma etching process |
US3986912A (en) * | 1975-09-04 | 1976-10-19 | International Business Machines Corporation | Process for controlling the wall inclination of a plasma etched via hole |
-
1976
- 1976-07-02 NL NL7607298A patent/NL7607298A/xx not_active Application Discontinuation
-
1977
- 1977-06-21 DE DE2727788A patent/DE2727788C2/de not_active Expired
- 1977-06-29 IT IT25218/77A patent/IT1081122B/it active
- 1977-06-29 CH CH800477A patent/CH630961A5/de not_active IP Right Cessation
- 1977-06-29 CA CA281,727A patent/CA1097434A/en not_active Expired
- 1977-06-29 JP JP52076682A patent/JPS6031100B2/ja not_active Expired
- 1977-06-29 GB GB27194/77A patent/GB1571034A/en not_active Expired
- 1977-07-01 FR FR7720247A patent/FR2356739A1/fr active Granted
-
1979
- 1979-06-13 US US06/047,979 patent/US4293375A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
NL7607298A (nl) | 1978-01-04 |
GB1571034A (en) | 1980-07-09 |
JPS6031100B2 (ja) | 1985-07-20 |
DE2727788A1 (de) | 1978-01-05 |
FR2356739B1 (it) | 1982-06-18 |
FR2356739A1 (fr) | 1978-01-27 |
JPS535974A (en) | 1978-01-19 |
CA1097434A (en) | 1981-03-10 |
CH630961A5 (de) | 1982-07-15 |
DE2727788C2 (de) | 1982-08-19 |
US4293375A (en) | 1981-10-06 |
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