IT7824657A0 - Metodo di fabbricazione di un dispositivo semiconduttore e dispositivo semiconduttore fabbricato con l'ausilio di tale metodo. - Google Patents

Metodo di fabbricazione di un dispositivo semiconduttore e dispositivo semiconduttore fabbricato con l'ausilio di tale metodo.

Info

Publication number
IT7824657A0
IT7824657A0 IT7824657A IT2465778A IT7824657A0 IT 7824657 A0 IT7824657 A0 IT 7824657A0 IT 7824657 A IT7824657 A IT 7824657A IT 2465778 A IT2465778 A IT 2465778A IT 7824657 A0 IT7824657 A0 IT 7824657A0
Authority
IT
Italy
Prior art keywords
semiconductor device
aid
manufacture
device manufactured
manufactured
Prior art date
Application number
IT7824657A
Other languages
English (en)
Other versions
IT1096489B (it
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IT7824657A0 publication Critical patent/IT7824657A0/it
Application granted granted Critical
Publication of IT1096489B publication Critical patent/IT1096489B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Local Oxidation Of Silicon (AREA)
IT24657/78A 1977-06-21 1978-06-16 Metodo di fabbricazione di un dispositivo semiconduttore e dispositivo semiconduttore fabbricato con l'ausilio di tale metodo IT1096489B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7706802A NL7706802A (nl) 1977-06-21 1977-06-21 Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.

Publications (2)

Publication Number Publication Date
IT7824657A0 true IT7824657A0 (it) 1978-06-16
IT1096489B IT1096489B (it) 1985-08-26

Family

ID=19828757

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24657/78A IT1096489B (it) 1977-06-21 1978-06-16 Metodo di fabbricazione di un dispositivo semiconduttore e dispositivo semiconduttore fabbricato con l'ausilio di tale metodo

Country Status (10)

Country Link
US (1) US4293588A (it)
JP (1) JPS548468A (it)
AU (1) AU518291B2 (it)
CA (1) CA1097432A (it)
CH (1) CH628756A5 (it)
DE (1) DE2826376A1 (it)
FR (1) FR2440076A1 (it)
GB (1) GB2000372B (it)
IT (1) IT1096489B (it)
NL (1) NL7706802A (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713744A (en) * 1980-06-30 1982-01-23 Fujitsu Ltd Manufacture of semiconductor device
US4337132A (en) * 1980-11-14 1982-06-29 Rockwell International Corporation Ion etching process with minimized redeposition
US4515652A (en) * 1984-03-20 1985-05-07 Harris Corporation Plasma sculpturing with a non-planar sacrificial layer
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
DE3603725C2 (de) * 1986-02-06 1994-08-18 Siemens Ag Verfahren zur Strukturierung von Siliciumcarbid
US5006480A (en) * 1988-08-08 1991-04-09 Hughes Aircraft Company Metal gate capacitor fabricated with a silicon gate MOS process
US4968641A (en) * 1989-06-22 1990-11-06 Alexander Kalnitsky Method for formation of an isolating oxide layer
US5258333A (en) * 1992-08-18 1993-11-02 Intel Corporation Composite dielectric for a semiconductor device and method of fabrication
DE29509545U1 (de) * 1995-06-10 1995-09-21 Voith Sulzer Papiermasch Gmbh Walze mit Schwingungsdämpfer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
US3472689A (en) * 1967-01-19 1969-10-14 Rca Corp Vapor deposition of silicon-nitrogen insulating coatings
US3607480A (en) * 1968-12-30 1971-09-21 Texas Instruments Inc Process for etching composite layered structures including a layer of fluoride-etchable silicon nitride and a layer of silicon dioxide
US3867216A (en) * 1972-05-12 1975-02-18 Adir Jacob Process and material for manufacturing semiconductor devices
US3795557A (en) * 1972-05-12 1974-03-05 Lfe Corp Process and material for manufacturing semiconductor devices
US3966501A (en) * 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
US3880684A (en) * 1973-08-03 1975-04-29 Mitsubishi Electric Corp Process for preparing semiconductor
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
DE2449731A1 (de) * 1973-12-03 1975-06-05 Hewlett Packard Co Aetzverfahren
JPS51126077A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Manufacturing method of semi-conductor equpment
NL7506594A (nl) * 1975-06-04 1976-12-07 Philips Nv Werkwijze voor het vervaardigen van een halfge- leiderinrichting en halfgeleiderinrichting ver- vaardigd met behulp van de werkwijze.
JPS5246784A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Process for production of semiconductor device
US3997367A (en) * 1975-11-20 1976-12-14 Bell Telephone Laboratories, Incorporated Method for making transistors
JPS5275989A (en) * 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device

Also Published As

Publication number Publication date
FR2440076B1 (it) 1983-11-25
CH628756A5 (de) 1982-03-15
AU518291B2 (en) 1981-09-24
US4293588A (en) 1981-10-06
GB2000372B (en) 1982-03-10
NL7706802A (nl) 1978-12-27
AU3724378A (en) 1980-01-03
FR2440076A1 (fr) 1980-05-23
DE2826376A1 (de) 1979-01-11
GB2000372A (en) 1979-01-04
JPS5653210B2 (it) 1981-12-17
IT1096489B (it) 1985-08-26
JPS548468A (en) 1979-01-22
CA1097432A (en) 1981-03-10

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