FR2440076A1 - Dispositif semi-conducteur et son procede de fabrication - Google Patents

Dispositif semi-conducteur et son procede de fabrication

Info

Publication number
FR2440076A1
FR2440076A1 FR7818372A FR7818372A FR2440076A1 FR 2440076 A1 FR2440076 A1 FR 2440076A1 FR 7818372 A FR7818372 A FR 7818372A FR 7818372 A FR7818372 A FR 7818372A FR 2440076 A1 FR2440076 A1 FR 2440076A1
Authority
FR
France
Prior art keywords
silicon
semiconductor device
silicon oxide
oxide
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7818372A
Other languages
English (en)
Other versions
FR2440076B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2440076A1 publication Critical patent/FR2440076A1/fr
Application granted granted Critical
Publication of FR2440076B1 publication Critical patent/FR2440076B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

UNE SURFACE D'UN CORPS EN SILICIUM EST SUCCESSIVEMENT MUNIE D'UNE COUCHE EN OXYDE DE SILICIUM ET D'UNE COUCHE EN NITRURE DE SILICIUM, APRES QUOI DES PARTIES DE LA SURFACE SONT DENUDEES ET SOUMISES A OXYDATION POUR OBTENIR UNE CONFIGURATION D'OXYDE ENFONCEE ET LES PARTIES SUBSISTANTES DE LA COUCHE EN NITRURE DE SILICIUM ET DE LA COUCHE EN OXYDE DE SILICIUM SOUS-JACENTE SONT ENLEVEES PAR DECAPAGE, CE QUI EFFECTUE DANS DES CONDITIONS TELLES QUE LE NITRURE DE SILICIUM EST PLUS RAPIDEMENT DECAPE QUE L'OXYDE DE SILICIUM ET LE SILICIUM ET L'OXYDE DE SILICIUM A PEU PRES AUSSI RAPIDEMENT QUE LE SILICIUM. APPLICATION : FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR.
FR7818372A 1977-06-21 1978-06-20 Dispositif semi-conducteur et son procede de fabrication Granted FR2440076A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7706802A NL7706802A (nl) 1977-06-21 1977-06-21 Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.

Publications (2)

Publication Number Publication Date
FR2440076A1 true FR2440076A1 (fr) 1980-05-23
FR2440076B1 FR2440076B1 (fr) 1983-11-25

Family

ID=19828757

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7818372A Granted FR2440076A1 (fr) 1977-06-21 1978-06-20 Dispositif semi-conducteur et son procede de fabrication

Country Status (10)

Country Link
US (1) US4293588A (fr)
JP (1) JPS548468A (fr)
AU (1) AU518291B2 (fr)
CA (1) CA1097432A (fr)
CH (1) CH628756A5 (fr)
DE (1) DE2826376A1 (fr)
FR (1) FR2440076A1 (fr)
GB (1) GB2000372B (fr)
IT (1) IT1096489B (fr)
NL (1) NL7706802A (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713744A (en) * 1980-06-30 1982-01-23 Fujitsu Ltd Manufacture of semiconductor device
US4337132A (en) * 1980-11-14 1982-06-29 Rockwell International Corporation Ion etching process with minimized redeposition
US4515652A (en) * 1984-03-20 1985-05-07 Harris Corporation Plasma sculpturing with a non-planar sacrificial layer
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
DE3603725C2 (de) * 1986-02-06 1994-08-18 Siemens Ag Verfahren zur Strukturierung von Siliciumcarbid
US5006480A (en) * 1988-08-08 1991-04-09 Hughes Aircraft Company Metal gate capacitor fabricated with a silicon gate MOS process
US4968641A (en) * 1989-06-22 1990-11-06 Alexander Kalnitsky Method for formation of an isolating oxide layer
US5258333A (en) * 1992-08-18 1993-11-02 Intel Corporation Composite dielectric for a semiconductor device and method of fabrication
DE29509545U1 (de) * 1995-06-10 1995-09-21 Voith Sulzer Papiermaschinen GmbH, 89522 Heidenheim Walze mit Schwingungsdämpfer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2240526A1 (fr) * 1973-08-03 1975-03-07 Mitsubishi Electric Corp
US3966501A (en) * 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
DE2616677A1 (de) * 1975-04-25 1976-11-04 Hitachi Ltd Verfahren zur herstellung einer halbleitervorrichtung mit flacher oberflaeche
FR2313770A1 (fr) * 1975-06-04 1976-12-31 Philips Nv Procede de fabrication d'un dispositif semi-conducteur, par nitridation, et dispositifs ainsi obtenus
NL7611057A (nl) * 1975-10-11 1977-04-13 Hitachi Ltd Werkwijze voor de vervaardiging van een halfgeleiderinrichting.

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
US3472689A (en) * 1967-01-19 1969-10-14 Rca Corp Vapor deposition of silicon-nitrogen insulating coatings
US3607480A (en) * 1968-12-30 1971-09-21 Texas Instruments Inc Process for etching composite layered structures including a layer of fluoride-etchable silicon nitride and a layer of silicon dioxide
US3795557A (en) * 1972-05-12 1974-03-05 Lfe Corp Process and material for manufacturing semiconductor devices
US3867216A (en) * 1972-05-12 1975-02-18 Adir Jacob Process and material for manufacturing semiconductor devices
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
DE2449731A1 (de) * 1973-12-03 1975-06-05 Hewlett Packard Co Aetzverfahren
US3997367A (en) * 1975-11-20 1976-12-14 Bell Telephone Laboratories, Incorporated Method for making transistors
JPS5275989A (en) * 1975-12-22 1977-06-25 Hitachi Ltd Production of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3966501A (en) * 1973-03-23 1976-06-29 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices
FR2240526A1 (fr) * 1973-08-03 1975-03-07 Mitsubishi Electric Corp
DE2616677A1 (de) * 1975-04-25 1976-11-04 Hitachi Ltd Verfahren zur herstellung einer halbleitervorrichtung mit flacher oberflaeche
FR2313770A1 (fr) * 1975-06-04 1976-12-31 Philips Nv Procede de fabrication d'un dispositif semi-conducteur, par nitridation, et dispositifs ainsi obtenus
NL7611057A (nl) * 1975-10-11 1977-04-13 Hitachi Ltd Werkwijze voor de vervaardiging van een halfgeleiderinrichting.
US4039359A (en) * 1975-10-11 1977-08-02 Hitachi, Ltd. Method of manufacturing a flattened semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/76 *

Also Published As

Publication number Publication date
CA1097432A (fr) 1981-03-10
GB2000372A (en) 1979-01-04
NL7706802A (nl) 1978-12-27
JPS5653210B2 (fr) 1981-12-17
AU3724378A (en) 1980-01-03
US4293588A (en) 1981-10-06
AU518291B2 (en) 1981-09-24
IT7824657A0 (it) 1978-06-16
IT1096489B (it) 1985-08-26
CH628756A5 (de) 1982-03-15
GB2000372B (en) 1982-03-10
FR2440076B1 (fr) 1983-11-25
JPS548468A (en) 1979-01-22
DE2826376A1 (de) 1979-01-11

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Legal Events

Date Code Title Description
ST Notification of lapse