KR920018850A - 메탈플러그의 형성방법 - Google Patents

메탈플러그의 형성방법 Download PDF

Info

Publication number
KR920018850A
KR920018850A KR1019920004598A KR920004598A KR920018850A KR 920018850 A KR920018850 A KR 920018850A KR 1019920004598 A KR1019920004598 A KR 1019920004598A KR 920004598 A KR920004598 A KR 920004598A KR 920018850 A KR920018850 A KR 920018850A
Authority
KR
South Korea
Prior art keywords
metal plug
forming
connection hole
formation method
insulating film
Prior art date
Application number
KR1019920004598A
Other languages
English (en)
Inventor
도시아끼 하세가와
쥰이찌 사또
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920018850A publication Critical patent/KR920018850A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

매탈플러그의 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 메탈플러그의 형성방법의 일예를 도시한 제조공정도(1).
제2도는 본원 발명의 메탈플러그의 형성방법의 일예를 도시한 제조공정도(2).
제3도는 본원 발명의 메탈플러그의 형성방법의 다른 제조공정을 도시한 설명도.

Claims (1)

  1. 절연막의 접속공내에 메탈플러그를 형성하는 방법에 있어서, 절연막의 표면에 밀착층을 형성하는 공정과, 레지스트마스크를 통해 상기 밀착층을 등방성에칭에 의해 이 레지스트마스크의 개구보다 큰 면적으로 제거하고, 또한 이방성에칭에 의해 상기 절연막에 접속공을 형성하는 공정과, 상기 접속공을 포함하여 메탈을 형성하고, 에치백하여 상기 접속공내에 메탈플러그를 형성하는 공정을 가지는 것을 특징으로 하는 메탈 플러그의 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920004598A 1991-03-22 1992-03-20 메탈플러그의 형성방법 KR920018850A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-58,931 1991-03-22
JP3058931A JPH04293233A (ja) 1991-03-22 1991-03-22 メタルプラグの形成方法

Publications (1)

Publication Number Publication Date
KR920018850A true KR920018850A (ko) 1992-10-22

Family

ID=13098582

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920004598A KR920018850A (ko) 1991-03-22 1992-03-20 메탈플러그의 형성방법

Country Status (3)

Country Link
US (1) US5374591A (ko)
JP (1) JPH04293233A (ko)
KR (1) KR920018850A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226742B1 (ko) * 1996-12-24 1999-10-15 구본준 반도체 소자의 금속배선 형성 방법

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545926A (en) * 1993-10-12 1996-08-13 Kabushiki Kaisha Toshiba Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts
JP2758841B2 (ja) * 1994-12-20 1998-05-28 日本電気株式会社 半導体装置の製造方法
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
KR100187666B1 (ko) * 1995-02-24 1999-06-01 김주용 반도체 소자의 텅스텐 플러그 형성방법
US5510296A (en) * 1995-04-27 1996-04-23 Vanguard International Semiconductor Corporation Manufacturable process for tungsten polycide contacts using amorphous silicon
US5607879A (en) * 1995-06-28 1997-03-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for forming buried plug contacts on semiconductor integrated circuits
US5545584A (en) * 1995-07-03 1996-08-13 Taiwan Semiconductor Manufacturing Company Unified contact plug process for static random access memory (SRAM) having thin film transistors
KR0172851B1 (ko) * 1995-12-19 1999-03-30 문정환 반도체 장치의 배선방법
KR100399966B1 (ko) * 1996-12-30 2003-12-24 주식회사 하이닉스반도체 반도체 소자 제조방법
US5981385A (en) * 1997-01-27 1999-11-09 Taiwan Semiconductor Manufacturing Company Ltd. Dimple elimination in a tungsten etch back process by reverse image patterning
US6271117B1 (en) 1997-06-23 2001-08-07 Vanguard International Semiconductor Corporation Process for a nail shaped landing pad plug
US5976976A (en) 1997-08-21 1999-11-02 Micron Technology, Inc. Method of forming titanium silicide and titanium by chemical vapor deposition
TW365700B (en) * 1997-10-17 1999-08-01 Taiwan Semiconductor Mfg Co Ltd Method of manufacture of plugs
US6143362A (en) * 1998-02-25 2000-11-07 Micron Technology, Inc. Chemical vapor deposition of titanium
US6284316B1 (en) 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
US6265305B1 (en) * 1999-10-01 2001-07-24 United Microelectronics Corp. Method of preventing corrosion of a titanium layer in a semiconductor wafer
KR100434508B1 (ko) * 2002-08-01 2004-06-05 삼성전자주식회사 변형된 듀얼 다마신 공정을 이용한 반도체 소자의 금속배선 형성방법
KR100665852B1 (ko) * 2005-08-03 2007-01-09 삼성전자주식회사 반도체 소자의 제조방법
KR100894769B1 (ko) * 2006-09-29 2009-04-24 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성방법
CN103515292B (zh) * 2012-06-19 2015-10-14 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN106773352A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 一种固化光罩及制作显示面板的方法
CN111564408B (zh) * 2020-04-29 2021-08-17 长江存储科技有限责任公司 一种开口的形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184024A (ja) * 1984-10-02 1986-04-28 Nec Corp 半導体装置の製造方法
JPS63182839A (ja) * 1987-01-23 1988-07-28 Nec Corp 半導体装置
JP2650313B2 (ja) * 1988-05-06 1997-09-03 松下電器産業株式会社 ドライエッチング方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226742B1 (ko) * 1996-12-24 1999-10-15 구본준 반도체 소자의 금속배선 형성 방법

Also Published As

Publication number Publication date
JPH04293233A (ja) 1992-10-16
US5374591A (en) 1994-12-20

Similar Documents

Publication Publication Date Title
KR920018850A (ko) 메탈플러그의 형성방법
KR920018851A (ko) 메탈플러그의 형성방법
KR910003752A (ko) 반도체장치의 제조방법
KR880013239A (ko) 반도체소자의 접속구멍형성 방법
KR920020619A (ko) 텅스텐플러그의 형성방법
KR920022456A (ko) 동 배선의 형성방법
KR880010495A (ko) 반도체장치의 제조방법
KR920013824A (ko) 레이저 다이오드 제조방법
KR920022422A (ko) 패턴 형성 방법
KR900002432A (ko) 반도체의 사이드벽 형성방법
KR920001678A (ko) 금속 배선의 알루미늄 산화막 형성 제조방법
KR920017212A (ko) 트렌치 형성방법
KR940015695A (ko) 반도체 소자의 패턴형성방법
KR930001497A (ko) 액정용 박막트랜지스터의 제조방법
KR910017619A (ko) 집적회로내 리액터 제조방법
KR920015469A (ko) 메탈 에칭(metal etch)시 메탈 증착방법
KR960026303A (ko) 미세패턴 형성방법
KR920015471A (ko) 반도체장치의 메탈 콘택 형성방법
KR970052836A (ko) 더미 배선을 갖춘 반도체 장치 및 그 제조 방법
KR940007611A (ko) 반도체 소자의 금속 배선 식각 방법
KR920015441A (ko) 반도체 소자의 노치현상 제거방법
KR940016870A (ko) 반도체 소자의 금속배선 형성방법
KR970023756A (ko) 반도체장치의 스페이서 형성방법
KR920015517A (ko) 딮 콘택트에서의 금속 배선 한정방법
KR910016050A (ko) 알루미늄막의 힐럭억제 방법

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid