KR880010495A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR880010495A
KR880010495A KR1019880001873A KR880001873A KR880010495A KR 880010495 A KR880010495 A KR 880010495A KR 1019880001873 A KR1019880001873 A KR 1019880001873A KR 880001873 A KR880001873 A KR 880001873A KR 880010495 A KR880010495 A KR 880010495A
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KR
South Korea
Prior art keywords
semiconductor device
film
forming
manufacturing
side wall
Prior art date
Application number
KR1019880001873A
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English (en)
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KR910000020B1 (ko
Inventor
도시요 이토
신이치 다카
지로 오시마
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR880010495A publication Critical patent/KR880010495A/ko
Application granted granted Critical
Publication of KR910000020B1 publication Critical patent/KR910000020B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 반도체장치의 제조방법에 있어서 그 일실시예에 따른 공정상의 단면도.
제2도는 제1도의 일부구조를 나타낸 평면도.
제3도는 각각 종래 반도체장치의 제조방법에 대한 다른 예를 나타낸 단면도이다.

Claims (1)

  1. 반도체장치 위에 제1막(5)을 형성시키는 제1공정과, 상기 제1막(5)에 제1구멍부(6)을 형성시키는 제2공정, 상기 제1구멍부(6)의 가장자리에 제1측벽(8)을 형성시키는 제3공정, 상기 제1측벽(8)에 의해 형성되어진 제2구멍부(8)에다 제2막(11)을 형성시키는 제4공정, 상기 제1측벽(8)을 제거해 주는 제5공정, 상기 제1막(5)과 상기 제2막(11)에 의해 형성되어진 제3구멍부(12)의 가장자리에다 제2측벽(13)을 형성시켜 주는 제6공정 및, 상기 제2측벽(13)에 의해 형성되어진 제4구멍부(14)에다 제3막(15)을 형성시키는 제7공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880001873A 1987-02-24 1988-02-23 반도체장치의 제조방법 KR910000020B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-39027 1987-02-24
JP62-039027 1987-02-24
JP62039027A JPS63207177A (ja) 1987-02-24 1987-02-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR880010495A true KR880010495A (ko) 1988-10-10
KR910000020B1 KR910000020B1 (ko) 1991-01-19

Family

ID=12541626

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880001873A KR910000020B1 (ko) 1987-02-24 1988-02-23 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US4910170A (ko)
JP (1) JPS63207177A (ko)
KR (1) KR910000020B1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967254A (en) * 1987-07-16 1990-10-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4971929A (en) * 1988-06-30 1990-11-20 Microwave Modules & Devices, Inc. Method of making RF transistor employing dual metallization with self-aligned first metal
US4988632A (en) * 1990-01-02 1991-01-29 Motorola, Inc. Bipolar process using selective silicon deposition
US5045483A (en) * 1990-04-02 1991-09-03 National Semiconductor Corporation Self-aligned silicided base bipolar transistor and resistor and method of fabrication
US5342808A (en) * 1992-03-12 1994-08-30 Hewlett-Packard Company Aperture size control for etched vias and metal contacts
EP0569745A1 (de) * 1992-05-14 1993-11-18 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Feldeffekttransistoren mit asymmetrischer Gate-Struktur
US6040604A (en) * 1997-07-21 2000-03-21 Motorola, Inc. Semiconductor component comprising an electrostatic-discharge protection device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696097A (en) * 1985-10-08 1987-09-29 Motorola, Inc. Poly-sidewall contact semiconductor device method
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
US4798928A (en) * 1987-03-26 1989-01-17 Foster Wheeler Energy Corporation Apparatus for tack welding a tube to a tubesheet
US4799990A (en) * 1987-04-30 1989-01-24 Ibm Corporation Method of self-aligning a trench isolation structure to an implanted well region

Also Published As

Publication number Publication date
JPH0513535B2 (ko) 1993-02-22
KR910000020B1 (ko) 1991-01-19
JPS63207177A (ja) 1988-08-26
US4910170A (en) 1990-03-20

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