KR920015471A - 반도체장치의 메탈 콘택 형성방법 - Google Patents
반도체장치의 메탈 콘택 형성방법 Download PDFInfo
- Publication number
- KR920015471A KR920015471A KR1019910000571A KR910000571A KR920015471A KR 920015471 A KR920015471 A KR 920015471A KR 1019910000571 A KR1019910000571 A KR 1019910000571A KR 910000571 A KR910000571 A KR 910000571A KR 920015471 A KR920015471 A KR 920015471A
- Authority
- KR
- South Korea
- Prior art keywords
- metal contact
- oxide film
- semiconductor device
- formation method
- film
- Prior art date
Links
- 239000002184 metal Substances 0.000 title claims 4
- 238000000034 method Methods 0.000 title claims 2
- 239000004065 semiconductor Substances 0.000 title claims 2
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 3
- 229920005591 polysilicon Polymers 0.000 claims 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도(a)~(d)는 본 발명에 따른 제조공정도이다.
Claims (1)
- 게이트 형성이 완료된 반도체장치에 있어서, 전면에 포토레지스트를 도포하고 메탈 콘택 형성영역을 노출시킨 후 전면에 폴리실리콘, 산화막을 차례로 스퍼터링하는 공정과, 메탈 콘택 형성영역이외의 상기 폴리실리콘, 상기 산화막을 리프트 오프공정으로 제거하고 전면에 제1 CVD산화막을 도포하는 공정과, 상기 제1산화막을 에치백하여 배리드 콘택을 내고 상기 배리드 콘택상에 커패시터를 형성하는 공정과, 전면에 제2CVD산화막, BPSG막을 차례로 도포하고 상기 폴리실리콘상의 상기 BPSG막, 상기 제2CVD산화막을 제거하여 메탈 콘택을 형성하는 공정으로 이루어진 반도체장치의 메탈 콘택 형성방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000571A KR930010670B1 (ko) | 1991-01-15 | 1991-01-15 | 반도체장치의 메탈 콘택 형성방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000571A KR930010670B1 (ko) | 1991-01-15 | 1991-01-15 | 반도체장치의 메탈 콘택 형성방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015471A true KR920015471A (ko) | 1992-08-26 |
| KR930010670B1 KR930010670B1 (ko) | 1993-11-05 |
Family
ID=19309840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910000571A KR930010670B1 (ko) | 1991-01-15 | 1991-01-15 | 반도체장치의 메탈 콘택 형성방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930010670B1 (ko) |
-
1991
- 1991-01-15 KR KR1019910000571A patent/KR930010670B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930010670B1 (ko) | 1993-11-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20051021 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |