KR940016503A - 텅스텐을 이용한 콘택플러그 제조방법 - Google Patents

텅스텐을 이용한 콘택플러그 제조방법 Download PDF

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Publication number
KR940016503A
KR940016503A KR1019920027092A KR920027092A KR940016503A KR 940016503 A KR940016503 A KR 940016503A KR 1019920027092 A KR1019920027092 A KR 1019920027092A KR 920027092 A KR920027092 A KR 920027092A KR 940016503 A KR940016503 A KR 940016503A
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KR
South Korea
Prior art keywords
metal layer
tungsten
via contact
contact hole
plug
Prior art date
Application number
KR1019920027092A
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English (en)
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KR960008550B1 (en
Inventor
최경근
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR92027092A priority Critical patent/KR960008550B1/ko
Priority to US08/174,880 priority patent/US5455198A/en
Publication of KR940016503A publication Critical patent/KR940016503A/ko
Application granted granted Critical
Publication of KR960008550B1 publication Critical patent/KR960008550B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/017—Clean surfaces

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 다층 금속간에 텅스텐을 이용한 콘택플러그 제조방법에 관한 것으로, 비아콘택홀에 F계 폴리머가 형성되는 것을 제거하기 위하여 비아콘택홀을 형성한 다음, 제 1 금속층 상부에 절연층을 형성하고 절연층의 소정부분을 식각하여 제 1 금속층이 노출된 비아콘택홀을 형성하는 단계와, 비아콘택홀 저부에 실리콘을 임플란트시킨후 텅스텐을 증착하여 비아콘택홀을 매립한 텅스텐 플러그를 형성하는 단계와, 제 2 금속층을 증착하여 텅스텐 플러그를 통해 제 1 금속층에 콘택하는 단계를 포함하는 기술이다.

Description

텅스텐을 이용한 콘택플러그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제 5 도는 본 발명에 의해 선택적 텅스텐을 이용한 콘택플러그 제조단계를 도시한 평면도.

Claims (3)

  1. 텅스텐을 이용한 콘택플러그 제조방법에 있어서, 제 1 금속층 상부에 절연층을 형성하고 절연층의 소정부분을 식각하여 제 1 금속층이 노출된 비아콘택홀을 형성하는 단계와, 비아콘택홀 저부에 실리콘을 임플란트시킨후 텅스텐을 증착하여 비아콘택홀을 매립한 텅스텐 플러그를 형성하는 단계와, 제 2 금속층을 증착하여 텅스텐 플러그를 통해 제 1 금속층에 콘택하는 단계를 포함하는 것을 특징으로 하는 텅스텐을 이용한 콘택플러그 제조방법.
  2. 제 1 항에 있어서, 상기 제 2 산화막은 IMO막 또는 SOG막으로 형성하는 것을 특징으로 하는 텅스텐을 이용한 콘택플러그 제조방법.
  3. 제 1 항에 있어서, 상기 제 1 금속층과 제 2 금속층은 알루미늄 합금으로 형성하는 것을 특징으로 하는 텅스텐을 이용한 콘택플러그 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR92027092A 1992-12-31 1992-12-31 Contact plug manufacturing method using tungsten KR960008550B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR92027092A KR960008550B1 (en) 1992-12-31 1992-12-31 Contact plug manufacturing method using tungsten
US08/174,880 US5455198A (en) 1992-12-31 1993-12-27 Method for fabricating tungsten contact plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92027092A KR960008550B1 (en) 1992-12-31 1992-12-31 Contact plug manufacturing method using tungsten

Publications (2)

Publication Number Publication Date
KR940016503A true KR940016503A (ko) 1994-07-23
KR960008550B1 KR960008550B1 (en) 1996-06-28

Family

ID=19348239

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92027092A KR960008550B1 (en) 1992-12-31 1992-12-31 Contact plug manufacturing method using tungsten

Country Status (2)

Country Link
US (1) US5455198A (ko)
KR (1) KR960008550B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5935869A (en) * 1997-07-10 1999-08-10 International Business Machines Corporation Method of planarizing semiconductor wafers
JP4390367B2 (ja) * 2000-06-07 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
KR100455724B1 (ko) * 2001-10-08 2004-11-12 주식회사 하이닉스반도체 반도체소자의 플러그 형성방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746621A (en) * 1986-12-05 1988-05-24 Cornell Research Foundation, Inc. Planar tungsten interconnect
JPS63205930A (ja) * 1987-02-21 1988-08-25 Ricoh Co Ltd 半導体集積回路装置の製造方法
JPS63260053A (ja) * 1987-04-16 1988-10-27 Nec Corp 半導体装置の製造方法
US4902645A (en) * 1987-08-24 1990-02-20 Fujitsu Limited Method of selectively forming a silicon-containing metal layer
JPH02144917A (ja) * 1988-11-28 1990-06-04 Hitachi Ltd リフトオフ法を利用した選拓的ｃｖｄ法によるタングステン膜形成方法
US4954214A (en) * 1989-01-05 1990-09-04 Northern Telecom Limited Method for making interconnect structures for VLSI devices
JPH02203531A (ja) * 1989-02-02 1990-08-13 Matsushita Electric Ind Co Ltd 多層配線の形成方法
JPH03190232A (ja) * 1989-12-20 1991-08-20 Fujitsu Ltd 半導体装置の製造方法
JP2519837B2 (ja) * 1991-02-07 1996-07-31 株式会社東芝 半導体集積回路およびその製造方法
JPH04354331A (ja) * 1991-05-31 1992-12-08 Sony Corp ドライエッチング方法
US5176790A (en) * 1991-09-25 1993-01-05 Applied Materials, Inc. Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal
US5305519A (en) * 1991-10-24 1994-04-26 Kawasaki Steel Corporation Multilevel interconnect structure and method of manufacturing the same

Also Published As

Publication number Publication date
US5455198A (en) 1995-10-03
KR960008550B1 (en) 1996-06-28

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