KR900019155A - 식각 베리어를 사용한 콘택 형성 방법 - Google Patents

식각 베리어를 사용한 콘택 형성 방법 Download PDF

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Publication number
KR900019155A
KR900019155A KR1019890007209A KR890007209A KR900019155A KR 900019155 A KR900019155 A KR 900019155A KR 1019890007209 A KR1019890007209 A KR 1019890007209A KR 890007209 A KR890007209 A KR 890007209A KR 900019155 A KR900019155 A KR 900019155A
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KR
South Korea
Prior art keywords
etch barrier
field oxide
insulating film
formation method
contact
Prior art date
Application number
KR1019890007209A
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English (en)
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KR920004541B1 (ko
Inventor
이원규
강미영
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890007209A priority Critical patent/KR920004541B1/ko
Priority to JP2139528A priority patent/JPH0756865B2/ja
Priority to US07/530,644 priority patent/US5063176A/en
Publication of KR900019155A publication Critical patent/KR900019155A/ko
Application granted granted Critical
Publication of KR920004541B1 publication Critical patent/KR920004541B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음

Description

식각 베리어를 사용한 콘택 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2d도는 본 발명의 공정방법에 의해 콘택홀을 형성하는 단계를 나타내는 단면도, 제3a도 및 3b도는 본 발명의 공정방법에 의해 콘택홀을 형성할 때 과다식각 또는 마스크오정렬이 발생하여도 절연막이 보호된 상태를 나타낸 단면도.

Claims (2)

  1. 실리콘 기판(1)상부에 필드 산화막(2)을 일정부분 형성하고 필드 산화막(2) 상부에 게이트 전극(3)을 형성하며, 필드 산화막(2) 사이의 실리콘 기판(1)에 확산층(4)을 형성하고, 게이트 전극(3)의 절연을 위하여 절연막(5)을 형성한 다음, 그 상부에 일정부분 도선(6)을 형성하고, 도선(6)을 보호하기 위해 상부에 절연막(7)을 형성한후 셀소자의 구조상 나타나는 굴곡을 완화하기 위한 BPSG 또는 PSG등의 절연막(9)을 증착하여 플로우시킨 다음, 콘택홀을 형성하는 것을 특징으로 하는 식각 베리어를 사용한 콘택형성방법.
  2. 제1항에 있어서, 상기 식각 베리어막을 질화막을 사용하여 형성하는 것을 특징으로 하는 식각 베리어를 사용한 콘택형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890007209A 1989-05-30 1989-05-30 반도체 소자에서 식각베리어층을 사용한 콘택홀 형성방법 KR920004541B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019890007209A KR920004541B1 (ko) 1989-05-30 1989-05-30 반도체 소자에서 식각베리어층을 사용한 콘택홀 형성방법
JP2139528A JPH0756865B2 (ja) 1989-05-30 1990-05-29 半導体素子の食刻バリヤー層を用いたコンタクトホール形成方法
US07/530,644 US5063176A (en) 1989-05-30 1990-05-30 Fabrication of contact hole using an etch barrier layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890007209A KR920004541B1 (ko) 1989-05-30 1989-05-30 반도체 소자에서 식각베리어층을 사용한 콘택홀 형성방법

Publications (2)

Publication Number Publication Date
KR900019155A true KR900019155A (ko) 1990-12-24
KR920004541B1 KR920004541B1 (ko) 1992-06-08

Family

ID=19286566

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890007209A KR920004541B1 (ko) 1989-05-30 1989-05-30 반도체 소자에서 식각베리어층을 사용한 콘택홀 형성방법

Country Status (3)

Country Link
US (1) US5063176A (ko)
JP (1) JPH0756865B2 (ko)
KR (1) KR920004541B1 (ko)

Families Citing this family (20)

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Publication number Priority date Publication date Assignee Title
US5275972A (en) * 1990-02-19 1994-01-04 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window
US5420077A (en) * 1990-06-29 1995-05-30 Sharp Kabushiki Kaisha Method for forming a wiring layer
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
EP0523856A3 (en) 1991-06-28 1993-03-17 Sgs-Thomson Microelectronics, Inc. Method of via formation for multilevel interconnect integrated circuits
KR950011986B1 (ko) * 1992-12-16 1995-10-13 현대전자산업주식회사 고집적 반도체 접속장치 제조방법
KR960009100B1 (en) * 1993-03-02 1996-07-10 Hyundai Electronics Ind Manufacturing method of minute contact hole for highly integrated device
US5498562A (en) * 1993-04-07 1996-03-12 Micron Technology, Inc. Semiconductor processing methods of forming stacked capacitors
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
EP0660392A1 (en) 1993-12-17 1995-06-28 STMicroelectronics, Inc. Method and interlevel dielectric structure for improved metal step coverage
US5439846A (en) * 1993-12-17 1995-08-08 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US5508218A (en) * 1993-12-28 1996-04-16 Lg Semicon Co., Ltd. Method for fabricating a semiconductor memory
US5670806A (en) * 1993-12-28 1997-09-23 Lg Semicon Co., Ltd. Semiconductor memory device
KR0138305B1 (ko) * 1994-11-30 1998-06-01 김광호 반도체소자 배선형성방법
US5607879A (en) * 1995-06-28 1997-03-04 Taiwan Semiconductor Manufacturing Company Ltd. Method for forming buried plug contacts on semiconductor integrated circuits
JP3592870B2 (ja) * 1996-12-26 2004-11-24 株式会社ルネサステクノロジ 半導体装置の製造方法
US6486527B1 (en) 1999-06-25 2002-11-26 Macpherson John Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter
US20050098480A1 (en) * 2003-11-12 2005-05-12 Robert Galiasso Hydrotreating catalyst and method
JP5373669B2 (ja) * 2010-03-05 2013-12-18 東京エレクトロン株式会社 半導体装置の製造方法

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Publication number Priority date Publication date Assignee Title
US4299862A (en) * 1979-11-28 1981-11-10 General Motors Corporation Etching windows in thick dielectric coatings overlying semiconductor device surfaces
JPS6072261A (ja) * 1983-09-28 1985-04-24 Fujitsu Ltd 半導体装置
JPS60198847A (ja) * 1984-03-23 1985-10-08 Nec Corp 半導体装置およびその製造方法
JPS60244072A (ja) * 1984-05-17 1985-12-03 Toshiba Corp 半導体装置の製造方法
US4560436A (en) * 1984-07-02 1985-12-24 Motorola, Inc. Process for etching tapered polyimide vias
JPS61179533A (ja) * 1985-02-05 1986-08-12 Fujitsu Ltd 半導体装置の製造方法
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
JPS61253834A (ja) * 1985-05-07 1986-11-11 Hitachi Ltd 半導体集積回路装置
EP0232508B1 (en) * 1986-01-09 1992-03-11 International Business Machines Corporation Dual glass reflow process for forming contacts
JPS6425551A (en) * 1987-07-22 1989-01-27 Toshiba Corp Semiconductor device
JPS6480067A (en) * 1987-09-19 1989-03-24 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof

Also Published As

Publication number Publication date
US5063176A (en) 1991-11-05
JPH0756865B2 (ja) 1995-06-14
KR920004541B1 (ko) 1992-06-08
JPH0329320A (ja) 1991-02-07

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