KR880011925A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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KR880011925A
KR880011925A KR1019880002226A KR880002226A KR880011925A KR 880011925 A KR880011925 A KR 880011925A KR 1019880002226 A KR1019880002226 A KR 1019880002226A KR 880002226 A KR880002226 A KR 880002226A KR 880011925 A KR880011925 A KR 880011925A
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film
forming
semiconductor device
insulating film
movable ion
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KR1019880002226A
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KR910008988B1 (ko
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마사키 사토
세이이치 모리
구니요시 요시가와
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아오이 죠이찌
가부시키가이샤 도시바
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Priority claimed from JP62220675A external-priority patent/JPS6464215A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
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Abstract

내용 없음

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도(A)~제2도는(G)는 본 발명의 1 실시예인 반도체장치의 제조방법을 설명하기 위한 각 공정에 따른 반도체장치의 단면도.
제3도(A)~제3도(E)는 본 발명의 다른 실시예인 반도체장치의 제조방법을 설명하기 위한 각 공정에 따른 단면도이다.

Claims (15)

  1. 반도체기판(101)상의 소자형성영역에 절연막(102)을 형성시키는 공정과, 상기 절연막(102)상에 가동이온게터막(109,110,122)을 형성시키는 공정, 상기 절연막(102) 및 게터막(109,110,122)을 에칭시켜 상기 반도체기판(101)이 노출되도록 접촉구멍(113,123)을 형성시키는 공정, SiO2막보다 양의 가동이온 저지막(114,124)을 상기 접촉구멍(113,123)의 내면을 포함하는 장치상을 형성시키는 공정, 상기 가동이온저지막을 에칭시켜서 접촉구멍의 측벽에 저지막을 남기는 공정 및, 상기 접촉구멍내에 금속배선을 형성시키는 공정으로 이루어진 것을 특징으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 절연막으로서 실리콘산화막을 형성시키는 공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 가동이온게터막으로서 인을 함유한 제1 PSG막을 형성시키는 공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제3항에 있어서, 가동이온저지막으로서 Si3N4막을 형성시키는 공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제3항에 있어서, 가동이온저지막으로서 인을 함유한 제2PSG막을 형성시키는 공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제3항에 있어서, 접촉구멍형성전에 상기 가동이온게터막에 의한 게터링공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제3항에 있어서, 접촉구멍 형성공정에는 에칭에 의해 접촉구멍측벽에 테이퍼를 형성시키는 공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제1항에 있어서, 상기 가동이온게 터막을 형성시키는 공정 또는 가동이온저지막을 형성시키는 공정중 적어도 한 공정후700°C이상의 열처리공정이 포함되어 있는 것을 특징으로 하는 반도체장치의 제조방법.
  9. 소자형성영역을 갖춘 반도체기판(101)과, 상기 소자형성영역상에 형성된 절연막(102), 상기 절연막 (102)상에 형성된 가동이온게터막(109,110,122), 상기 절연막 및 게터막을 통해서 가판표면이 노출되도록 형성된 접촉구멍(113,123), 상기 접촉구멍(113,123)의 내면에다 그 아랫면을 제외하고 형성시켜서 SiO2보다 양의 가동이온이 통과하기어렵게 만드는 가동이온저지막(114,124) 및, 상기 접촉구멍내에 형성되어 그 아랫면에서 기판과 전기적으로 접속되어지는 금속배선(115,116)을 구비하여 구성된 것을 특징으로 하는 반도체장치.
  10. 제10항에 있어서, 절연막은 실리콘산화막인 것을 특징으로 하는 반도체장치.
  11. 제11항에 있어서, 가동이온게터막은 인을 함유한 제1PSG막인 것을 특징으로 하는 반도체장치.
  12. 제11항에 있어서, 가동이온저지막은 Si3N4막인 것을 특징으로 하는 반도체장치.
  13. 제11항에 있어서, 가동이온저지막은 인을 함유한 제2PSG막인 것을 특징으로 하는 반도체장치.
  14. 제13항에 있어서, 상기 제2PSG막은 접촉구멍측벽에서 형성된 테이퍼부를 구비하고 있음을 특징으로 하는 반도체장치.
  15. 반도체기판(101)에 형성된 불휘발성 반도체 메모리셀과, 상기 메모리셀을 덮는 층간절연막(109,110,122), 상기 절연막에 설치된 접촉구멍(113,123), 상기 접촉구멍을 통과하는 금속배선층(115,126), 상기 금속배선층(115,126)과 상기 접촉구멍(113,123)의 내벽사이에 설치되어 층간절연막보다 양의 가동이온이 통과하기어렵게 만드는 층(114,124)을 구비하여 구성된 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880002226A 1987-03-04 1988-03-04 반도체장치 및 그 제조방법 KR910008988B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP62-047731 1987-03-04
JP62-47731 1987-03-04
JP62047731A JPS63215080A (ja) 1987-03-04 1987-03-04 不揮発性半導体メモリ及びその製造方法
JP62-220675 1987-09-03
JP62220675A JPS6464215A (en) 1987-09-03 1987-09-03 Manufacture of semiconductor device

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KR880011925A true KR880011925A (ko) 1988-10-31
KR910008988B1 KR910008988B1 (ko) 1991-10-26

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US (1) US5679590A (ko)
EP (1) EP0281140B1 (ko)
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DE (1) DE3880860T2 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0642168B1 (en) * 1989-07-18 1998-09-23 Sony Corporation Non-volatile semiconductor memory device
US5294295A (en) * 1991-10-31 1994-03-15 Vlsi Technology, Inc. Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges
US5418173A (en) * 1992-11-24 1995-05-23 At&T Corp. Method of reducing ionic contamination in integrated circuit fabrication
US6008544A (en) * 1992-12-08 1999-12-28 Fujitsu Limited Semiconductor device and manufacturing method of the semiconductor device
FR2708146A1 (fr) * 1993-07-19 1995-01-27 Sgs Thomson Microelectronics Cellule à grille flottante à durée de stockage accrue.
US7172864B1 (en) * 1993-11-01 2007-02-06 Nanogen Methods for electronically-controlled enzymatic reactions
US5953635A (en) * 1996-12-19 1999-09-14 Intel Corporation Interlayer dielectric with a composite dielectric stack
US6093302A (en) 1998-01-05 2000-07-25 Combimatrix Corporation Electrochemical solid phase synthesis
AU2003200747B2 (en) * 1998-01-05 2006-11-23 Combimatrix Corporation Gettering device for ion capture
US6335249B1 (en) * 2000-02-07 2002-01-01 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
WO2003031362A1 (en) 2001-10-05 2003-04-17 Dow Global Technologies Inc. Coated glass for use in displays and other electronic devices
CN111508835A (zh) * 2020-04-26 2020-08-07 深圳市昭矽微电子科技有限公司 图形结构及其形成方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927110B2 (ja) * 1975-08-22 1984-07-03 セイコーエプソン株式会社 半導体装置の製造方法
JPS5492175A (en) * 1977-12-29 1979-07-21 Fujitsu Ltd Manufacture of semiconductor device
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
JPS5519850A (en) * 1978-07-31 1980-02-12 Hitachi Ltd Semiconductor
JPS5534444A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4376947A (en) * 1979-09-04 1983-03-15 Texas Instruments Incorporated Electrically programmable floating gate semiconductor memory device
US4309812A (en) * 1980-03-03 1982-01-12 International Business Machines Corporation Process for fabricating improved bipolar transistor utilizing selective etching
JPS57126147A (en) * 1981-01-28 1982-08-05 Fujitsu Ltd Manufacture of semiconductor device
DE3133516A1 (de) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum verrunden des zwischenoxids zwischen polysiliziumebene und metall-leiterbahnebene beim herstellen von integrierten n-kanal-mos-feldeffekttransistoren
JPS58166766A (ja) * 1982-03-27 1983-10-01 Fujitsu Ltd 半導体装置の製造方法
US4489481A (en) * 1982-09-20 1984-12-25 Texas Instruments Incorporated Insulator and metallization method for VLSI devices with anisotropically-etched contact holes
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
US4763177A (en) * 1985-02-19 1988-08-09 Texas Instruments Incorporated Read only memory with improved channel length isolation and method of forming
JPS62125679A (ja) * 1985-11-26 1987-06-06 Nec Corp Ｍｏｓ半導体記憶装置

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KR910008988B1 (ko) 1991-10-26
EP0281140A3 (en) 1989-08-02
EP0281140A2 (en) 1988-09-07
US5679590A (en) 1997-10-21
DE3880860D1 (de) 1993-06-17
DE3880860T2 (de) 1993-10-28
EP0281140B1 (en) 1993-05-12

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