KR960006066A - BiMOS반도체장치 및 그 제조방법 - Google Patents

BiMOS반도체장치 및 그 제조방법 Download PDF

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Publication number
KR960006066A
KR960006066A KR1019950019234A KR19950019234A KR960006066A KR 960006066 A KR960006066 A KR 960006066A KR 1019950019234 A KR1019950019234 A KR 1019950019234A KR 19950019234 A KR19950019234 A KR 19950019234A KR 960006066 A KR960006066 A KR 960006066A
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South Korea
Prior art keywords
conductive layer
layer
insulating film
mos transistor
semiconductor device
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KR1019950019234A
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English (en)
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이꾸오 요시하라
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이데이 노브유끼
소니 가부시끼가이샤
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Publication of KR960006066A publication Critical patent/KR960006066A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명의 목적은, 바이폴러 트랜지스터의 고속동작 및 고신뢰성을 실현하는 동시에 MOS트랜지스터에 있어서도 신뢰성의 저하를 방지하는데 있다.
그 구성은 베이스전극인 다결정 Si(23a)과 에미터전극인 폴리사이드층 (68a)과는 개구부(35)의 내측면에 있어서의 측벽으로 되어 있는 SiO2층(36a)과 SiO2층(36a)과 SiO2층(34a)에서 전기적으로 분리되어 있으나 SiO2층(34a)은 SiO2층 (36a)으로 이루는 측벽을 형성할 때의 오프셋용으로도 되어 있으므로 SiO2층(34a)은 막두께가 두껍다.그러나 이 SiO2층(34a)은 MOS트랜지스터(13)에는 설치되어 있지 않으므로 MOS트랜지스터(13)에서는 단차가작다.

Description

BiMOS반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예를 나타내는 측단면도이다.
제2도는 일실시예를 제조하기 위한 최초의 공정을 순차로 나타내는 측단면도이다.

Claims (4)

  1. 바이폴러 트랜지스터와 MOS트랜지스터와를 동일의 반도체 기체에 포함하는 BiMOS반도체장치에 있어서, 상기 바이폴러 트랜지스터의 베이스전극용의 도전층을 덮는 절연막위에 에미터전극용의 도전층이 설치되어 있고, 상기 MOS트랜지스터에는 상기 절연막이 설치되어 있지 않은 것을 특징으로 하는 BiMOS반도체장치.
  2. 제1항에 있어서, 상기 반도체 기체위의 제1층째의 도전층에서 상기 MOS트랜지스터의 게이트전극이 형성되어 있고, 상기 반도체 기체위의 제2층째의 도전층에서 상기 베이스전극이 형성되어 있고, 상기 반도체 기체위의 제3층째의 도전층에서 상기 MOS트랜지스터의 배선과 상기 에미터전극이 형성되어 있고, 상기 절연막이 상기 제2층째의 도전층과 상기 제3층째의 도전층과의 사이의 충간절연막으로 되어 있는 것을 특징으로 하는 BiMOS반도체장치.
  3. 제항 또는 제2항에 있어서, 상기 베이스전극용의 도전층과 이 베이스전극용 도전층위의 제1절연막을 관통하는 개구부의 내측면에 제2절연막으로 이루는 측벽이 설치되어 있고, 상기 에미터전극용 도전층의 상기 측벽의 내측에 넓혀져 있고, 상기 MOS트랜지스터에는 상기 제1절연막이 설치되어 있지 않은 것을 특징으로 하는 BiMOS반도체장치.
  4. 제1항 내지 제3항 중 어느 1항에 있어서, 상기 베이스전극용의 도전층과 이 도전층위의 절연막과를 순차로 전면에 형성하는 공정과, 상기 도전층을 에칭종점으로 하여 적어도 상기 MOS트랜지스터의 형성영역에 있어서의 상기 절연막을 에칭하는 공정과를 구비하는 것을 특징으로 하는 BiMOS반도체장치.
    ※참고사항:최초출원 내용에 의하여 공개하는 것임.
KR1019950019234A 1994-07-29 1995-07-01 BiMOS반도체장치 및 그 제조방법 KR960006066A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-197763 1994-07-29
JP19776394A JP3282172B2 (ja) 1994-07-29 1994-07-29 ＢｉＭＯＳ半導体装置の製造方法

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KR960006066A true KR960006066A (ko) 1996-02-23

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US (1) US5789285A (ko)
EP (1) EP0694972A3 (ko)
JP (1) JP3282172B2 (ko)
KR (1) KR960006066A (ko)

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* Cited by examiner, † Cited by third party
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US6001701A (en) * 1997-06-09 1999-12-14 Lucent Technologies Inc. Process for making bipolar having graded or modulated collector
CN1263637A (zh) * 1997-07-11 2000-08-16 艾利森电话股份有限公司 制作用于射频的集成电路器件的工艺
US6611044B2 (en) 1998-09-11 2003-08-26 Koninklijke Philips Electronics N.V. Lateral bipolar transistor and method of making same
DE60040812D1 (de) * 1999-03-15 2008-12-24 Matsushita Electric Ind Co Ltd Herstellungsverfahren für einen Bipolar-Transistor und ein MISFET Halbleiter Bauelement
US6492211B1 (en) 2000-09-07 2002-12-10 International Business Machines Corporation Method for novel SOI DRAM BICMOS NPN
JP4056218B2 (ja) * 2000-12-27 2008-03-05 三洋電機株式会社 半導体装置およびその製造方法

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US5093707A (en) * 1988-04-27 1992-03-03 Kabushiki Kaisha Toshiba Semiconductor device with bipolar and cmos transistors
US5204276A (en) * 1988-12-06 1993-04-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US4994400A (en) * 1989-01-27 1991-02-19 Tektronix, Inc. Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls
JPH0348457A (ja) * 1989-04-14 1991-03-01 Toshiba Corp 半導体装置およびその製造方法
JP2913785B2 (ja) * 1990-07-12 1999-06-28 富士通株式会社 半導体装置の製造方法
JP2625602B2 (ja) * 1991-01-18 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 集積回路デバイスの製造プロセス
KR940003589B1 (ko) * 1991-02-25 1994-04-25 삼성전자 주식회사 BiCMOS 소자의 제조 방법
KR930009111A (ko) * 1991-10-24 1993-05-22 와가 노리오 바이폴라트랜지스터, Bi-CMOS 장치 및 그 제조방법
JPH05226589A (ja) * 1992-02-17 1993-09-03 Mitsubishi Electric Corp Ｃ−ＢｉＣＭＯＳ型半導体装置およびその製造方法
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EP0694972A3 (en) 1997-01-08
JPH0846068A (ja) 1996-02-16
EP0694972A2 (en) 1996-01-31
JP3282172B2 (ja) 2002-05-13
US5789285A (en) 1998-08-04

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