KR960020643A - 스택 가능형 회로 기판층의 제조 방법 - Google Patents

스택 가능형 회로 기판층의 제조 방법 Download PDF

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KR960020643A
KR960020643A KR1019950042211A KR19950042211A KR960020643A KR 960020643 A KR960020643 A KR 960020643A KR 1019950042211 A KR1019950042211 A KR 1019950042211A KR 19950042211 A KR19950042211 A KR 19950042211A KR 960020643 A KR960020643 A KR 960020643A
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South Korea
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forming
circuit board
metal
stackable
layer
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KR1019950042211A
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KR100229572B1 (ko
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알버트 프랭케니 제롬
프란시스 프랭케니 리챠드
란 임켄 로널드
앨런 밴더리 케니스
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윌리엄 티. 엘리스
인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
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    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H05K2201/09—Shape and layout
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    • H05K2201/0929—Conductive planes
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    • H05K2201/095—Conductive through-holes or vias
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    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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    • H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
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    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S428/00—Stock material or miscellaneous articles
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  • Computer Hardware Design (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract

본 발명의 목적은 전력 분배, 신호 분배 및 용량성 감결합을 제공하는 박편스택 가능형 기판층을 포함한 미소 피치 패턴의 다층 인쇄 회로 기판을 제조하기 위한 방법 및 장치를 제공하는 데 있다. 일실시예의 경우, 본 발명은 금속 코어에서 시작하고, 코어를 패터닝하고, 코어를 유전체로 선택적으로 침착시키고, 비어 및 플러그 상에 결합 야금과 함께 덴드라이트를 형성시킴으로써 기판 상의 평면 위 또는 아래로부터 스택 가능형 연결을 제공하는 기판층의 제조에 관한 것이다. 다른 실시예에서는, 본 발명은 금속 시트 상에 박막의 고유전율 결정막을 형성하고 이어서 고유전율 결정막 상에 금속층을 침착시키기 위한 졸-겔 처리의 사용에 관한 것이다. 고유전율 결정막은 캐패시터층의 유전체로서 작용하여, 그 후에 연속하여 패턴화되고, 유전체에 의해 피복되고, 캐패시터를 상호 연결시키고 비어를 형성하기 위한 금속층이 선택적으로 침착되어 있다. 다음에 비어들의 단부들은 덴드라이트 성장 및 결합 야금 처리를 받아 스택 가능형 상호 연결 능력이 제공된다. 금속 코어를 갖는 층들과 용량성으로 구성된 코어를 갖는 층들을 적절하게 사용하여 다층의 복합 박편 스택 가능형 회로 기판 구조체를 제조한다. 다층의 박편 스택 가능형 회로 기판 구조체는 표면 실장형 전자 회로 소자들과 복합 회로 기판의 전력, 신호 및 용량성 감결합 층돌 간에 비어 및 플러그 형성의 텐드라이트 및 결합 야금을 통한 직접 수직 연결을 제공한다.

Description

스택 가능형 회로 기판층의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 전력 평면 및 신호 라인을 갖는 회로 기판층의 제조 중에 여러 단계에서의 개략적인 횡단면도.

Claims (8)

  1. 스택 가능형 회로 기판층(shakable circuit board layer)을 제조하는 방법에 있어서, 금속 시트(metallic sheet)중에 구멍들(hole)을 형성하는 단계와, 상기 금속 시트 상에 제1유전층(a first dielectric layer)을 형성하는 단계와, 상기 제1유전층의 제1 및 제2위치(at respective first and second locations)에서 제1 및 제2구멍을 형성하는 단계와, 상기 제1 및 제2위치에 금속 침착물을 선택적으로 형성하는 단계로서, 상기 제1위치에서의 금속 침착물은 상기 제1유전층에 의해 상기 금속 시트와 전기 전연되는 비어(via)를 형성하며, 상기 제2위치에서의 금속 침착물은 상기 금속 시트와 전기 접속되는 비어를 형성하게 되는 금속 침착물의 선택적 형성 단계와, 상기 비어들의 단부들에서 덴드라이트(dendrites)를 형성하는 단계를 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  2. 제1항에 있어서, 상기 덴드라이트 상에 결합 야금(a joining metallurgy)을 형성하는 단계를 더 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  3. 제2항에 있어서, 상기 금속 침착물의 선택적 형성 단계는 상기 금속 시트의 상기 제1유전층 중 비선택 영역을 마스킹(masking)하는 단계와, 상기 마스킹 단계 중에 피복되지 않은 영역 상에 상기 금속을 도금(planting)하는 단계를 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  4. 제3항에 있어서, 상기 도금 단계 전에 공통층(a commoning layer)을 형성하는 단계와, 상기 도금 단계 후에 노출된 공통층을 제거시키는 단계를 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  5. 제2항에 있어서, 상기 금속 시트는 구리-인바-구리 합성물(a copper-invar-copper composition)을 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  6. 제1항에 있어서, 상기 금속 침착물의 선택적 형성 단계는 상기 제1 및 제2위치에서의 상기 금속 침착물과는 전기적으로 절연하여 상기 제1유전층 상의 제3위치에서 금속 침착물의 형성을 제공하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  7. 제2항에 있어서, 상기 덴드라이트 형성 단계는 상기 비어들의 단부들 이외의 영역들을 선택적으로 마스킹하는 단계와, 마스크되지 않은 마스크되지 않은 영역들을 덴드라이트로 성장시키는 단계를 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
  8. 제6항에 있어서, 상기 덴드라이트 형성 단계는 상기 비어들의 단부들 이외의 영역들을 선택적으로 마스킹하는 단계와, 마스크되지 않은 영역들을 텐드라이트로 성장시키는 단계를 포함하는 것을 특징으로 하는 스택 가능형 회로 기판층의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950042211A 1994-11-21 1995-11-20 스택가능형 층상회로기판 구조의제조방법 KR100229572B1 (ko)

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US5509200A (en) 1996-04-23

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