KR940702312A - 박막 트랜지스터, 고체장치, 표시장치 및, 박막 트랜지스터의 제조방법(Thin film transistor, solid device, display device and manufacturing mothed of a thin film transistor) - Google Patents
박막 트랜지스터, 고체장치, 표시장치 및, 박막 트랜지스터의 제조방법(Thin film transistor, solid device, display device and manufacturing mothed of a thin film transistor)Info
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- KR940702312A KR940702312A KR1019940700563A KR19940700563A KR940702312A KR 940702312 A KR940702312 A KR 940702312A KR 1019940700563 A KR1019940700563 A KR 1019940700563A KR 19940700563 A KR19940700563 A KR 19940700563A KR 940702312 A KR940702312 A KR 940702312A
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- Prior art keywords
- thin film
- film transistor
- region
- low concentration
- transistor according
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- 239000010409 thin film Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract 6
- 239000007787 solid Substances 0.000 title claims 2
- 239000010408 film Substances 0.000 claims abstract 24
- 239000012535 impurity Substances 0.000 claims abstract 12
- 238000000034 method Methods 0.000 claims abstract 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract 9
- 239000010703 silicon Substances 0.000 claims abstract 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 8
- 238000002425 crystallisation Methods 0.000 claims abstract 7
- 230000008025 crystallization Effects 0.000 claims abstract 7
- 239000000758 substrate Substances 0.000 claims 6
- 239000011159 matrix material Substances 0.000 claims 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims 1
- 238000000137 annealing Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 claims 1
- 239000000470 constituent Substances 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 238000005224 laser annealing Methods 0.000 claims 1
- 239000007790 solid phase Substances 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
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- H01L29/772—Field effect transistors
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
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Abstract
본 발명은 오프 전류 특성과 같은 전기적 특성을 향상시키는 박막 트랜지스터와, 박막 트랜지스터의 제조 방법에 관한 것이다. 박막 트랜지스터(110)는 약 400A의 n-실리콘막(저농도 영역)으로 구성된 n-소스 영역(112)과 n-드레인 영역(113)을 가지며, 이는 비정질 실리콘에 SCP 법과 같은 결정화 처리를 실행함으로써 만들어진 실리콘막이고, 결정화처리는 불순물 도입 이후에 불순물의 활성화를 실행한다. 게이트 전극(116)은 금속 전극이고, n-소스 영역(112)과 n-드레인 영역(113)이 형성된 후에 형성된다. 게이트 전극(116), n-소스 영역(112) 및 n-드레인 영역(113)은 자동 정렬적으로 형성되지 않는다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 박막 트랜지스터의 구조를 도시한 단면도, 제2A도는 제1도에 도시한 박막 트랜지스터의 오프 전류 특성을 도시한 그래프, 제2B도는 비교 실시예에 따른 박막 트랜지스터의 오프 전류 특성을 도시한 그래프, 제3A도는 제1도에 도시한 박막 트랜지스터의 기생 용량을 도시한 설명도, 제3B도는 비교 실시예에 따른 박막 트랜지스터의 기생 용량을 도시한 설명도.
Claims (22)
- 기판의 표면상에 소스 영역과 드레인 영역 사이에 채널을 형성할 수 있는 채널 영역과, 채널 영역의 표면상의 게이트 절연막을 통해서 상기 채널 영역과 직면하는 게이트 전극을 포함하며, 상기 소스 영역과 상기 드레인 영역에서 상기 게이트 전극의 단부를 상기 게이트 절연막을 통해서 중복시키는 영역은 게이트 전극이 형성되는 공정보다 앞선 공정으로 형성된 저농도 영역인 것을 특징으로 하는 박막 트랜지스터.
- 제1항에 있어서, 저농도 영역의 불수물 농도는 1×1020cm-3보다 적거나 같은 것을 특징으로 하는 박막 트랜지스터.
- 제1항 또는 제2항에 있어서, 상기 저농도 영역은 불순물이 상기 기판의 표면상에 형성된 실리콘막에 도입된 후에 결정화 처리가 실시되는 영역인 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제3항중 어느 한 항에 있어서, 상기 소스 영역과 상기 드레인 영역은 고불순물 농도를 갖는 상기 각 저농도 영역에 접속되는 저 레지스트 영역을 가지는 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제3항중 어느 한 항에 있어서, 상기 소스 영역과 상기 드레인 영역은 상기 저농도 영역의 막보다 더 두꺼운 막을 갖는 상기 저농도 영역에 접속되는 저 레지스트 영역을 가지는 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제5항중 어느 한 항에 있어서, 상기 채널, 영역과, 상기 저 레지스트 영역의 소스 영역 및 드레인 영역은 다른 공정으로 형성된 영역인 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제6항중 어느 한 항에 있어서, 상기 저농도 영역의 막 두께는 상기 채널 영역의 막 두께와 동일한 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제7항중 어느 한 항에 있어서, 상기 저농도 영역의 막 두께는 상기 게이트 전극에 전위가 인가될 때 상기 막 두께가 저농도 영역의 불순물 농도에 의해 결정되는 상태로 형성된 공핍층보다 더 얇은 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제8항중 어느 한 항에 있어서, 상기 저농도 영역의 막 두께는 500Å보다 얇거나 동일한 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제8항중 어느 한 항에 따른 박막 트랜지스터를 갖는 것을 특징으로 하는 박막 트랜지스터.
- 제1항 내지 제9항중 어느 한 항에 따른 박막 트랜지스터와, 상기 박막 트랜지스터에 대해서 역도전형이고 그 소스 영역과 드레인 영역이 게이트 전극에 대해 자동 정렬적으로 형성되는 박막 트랜지스터로 구성된 CMOS 회로를 포함하는 것을 특징으로 하는 고체장치.
- 활성 매트릭스 배열의 화소 트랜지스터와 같은 제1항 내지 제9항중 어느 한 항에 따른 박막 트랜지스터를 포함하는 것을 특징으로 하는 표시 장치.
- 제12항에 있어서, 상기 드레인 영역은 그 구성부분과 동시에 형성되고 선행상태의 주사선 사이에 저장 용량을 형성하는 연장 영역을 가지는 것을 특징으로 하는 표시 장치.
- 제12항 또는 제13항에 있어서, 상기 활성 매트릭스 배열과 함께 동일 기판상에 형성된 구동회로에서 그 CMOS 회로가 상기 박막 트랜지스터와 같은 비자동 정렬 구조를 갖는 박막 트랜지스터와, 박막 트랜지스터에 대해서 도전형이 역전되고 게이트 전극에 대해 자동 정렬적으로 형성된 박막 트랜지스터를 가지는 것을 특징으로 하는 표시 장치.
- 제12항 또는 제13항에 있어서, 상기 활성 매트릭스 배열과 함께 동일 기판상에 형성된 구동회로에서 그 CMOS 회로가 상기 박막 트랜지스터와 같은 자동 정렬적으로 형성된 n채널형 박막 트랜지스터와 p채널형 박막 트랜지스터를 가지는 것을 특징으로 하는 표시 장치.
- 제14항 또는 제15항에 있어서, 상기 기판상에 형성된 박막 트랜지스터중에, 상기 자동 정렬 박막 트랜지스터의 소스 영역과 드레인 영역의 막 두께는 상기 비자동 정렬 박막 트랜지스터의 저농도 영역의 막 두께와 동일한 것을 특징으로 하는 표시 장치.
- 제14항 내지 제16항중 어느 한 항에 있어서, 상기 자동 정렬 박막 트랜지스터의 소스 영역과 드레인 영역은 약 1×1023cm-3이상의 불순물 농도를 가지는 반면에, 상기 비자동 정렬 박막 트랜지스터의 상기 저농도 영역은 약 1×1023cm-3이하의 불순물 농도를 가지는 것을 특징으로 하는 표시 장치.
- 제1항에 따른 박막 트랜지스터의 제조방법에 있어서, 상기 저농도 영역이 상기 기판상의 표면상에 형성되는 공정은 상기 게이트 전극이 형성되는 공정전에 실행되는 것을 특징으로 하는 표시 장치.
- 제18항에 있어서, 불순물이 상기 실리콘막 내부에 도입된 후에 실리콘막상에 인가된 결정화 처리가 불순물을 활성화하도록 적어도 상기 저농도 영역을 형성하기 위해 실리콘막을 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조 방법.
- 제18항에 있어서, 상기 결정화 처리는 상기 실리콘막에 대해서 레이저 비임을 조사해서 상기 막을 결정화함과 동시에 상기 막 내부에서 불순물을 활성화시키는 레이져 어닐링법인 것을 특징으로 하는 박막 트랜지스터의 제조 방법.
- 제18항에 있어서, 상기 결정화 처리는 상기 실리콘막이 저온에서 장시간 동안 어닐링되어 상기 막을 결정화함과 동시에 상기 막 내부에서 불순물을 활성화시키는 고상 성장법인 것을 특징으로 하는 박막 트랜지스터의 제조 방법.
- 제18항에 있어서, 상기 결정화 처리는 상기 실리콘막이 램프 어닐링되어 상기 막을 결정화함과 동시에 상기 막 내부에서 불순물을 활성화시키는 고속 열 어닐링법인 것을 특징으로 하는 박막 트랜지스터의 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
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JP92-166021 | 1992-06-24 | ||
JP16602192 | 1992-06-24 | ||
JP92-315331 | 1992-11-25 | ||
JP31533192 | 1992-11-25 | ||
JP92-325315 | 1992-12-04 | ||
JP32531592 | 1992-12-04 | ||
PCT/JP1993/000849 WO1994000882A1 (en) | 1992-06-24 | 1993-06-23 | Thin film transistor, solid-state device, display device, and method for manufacturing thin film transistor |
Publications (2)
Publication Number | Publication Date |
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KR940702312A true KR940702312A (ko) | 1994-07-28 |
KR100309934B1 KR100309934B1 (ko) | 2002-06-20 |
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KR1019940700563A KR100309934B1 (ko) | 1992-06-24 | 1993-06-23 | 박막트랜지스터,고체장치,표시장치,및박막트랜지스터의제조방법 |
Country Status (6)
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US (2) | US5508216A (ko) |
EP (1) | EP0602250B1 (ko) |
KR (1) | KR100309934B1 (ko) |
DE (1) | DE69326123T2 (ko) |
TW (1) | TW268133B (ko) |
WO (1) | WO1994000882A1 (ko) |
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- 1993-06-23 WO PCT/JP1993/000849 patent/WO1994000882A1/ja active IP Right Grant
- 1993-06-23 KR KR1019940700563A patent/KR100309934B1/ko not_active IP Right Cessation
- 1993-06-23 DE DE69326123T patent/DE69326123T2/de not_active Expired - Lifetime
- 1993-06-23 US US08/199,185 patent/US5508216A/en not_active Expired - Lifetime
- 1993-06-23 EP EP93913567A patent/EP0602250B1/en not_active Expired - Lifetime
- 1993-07-21 TW TW082105812A patent/TW268133B/zh not_active IP Right Cessation
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- 1997-06-24 US US08/881,097 patent/US5757048A/en not_active Expired - Lifetime
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KR100623230B1 (ko) * | 2003-11-29 | 2006-09-18 | 삼성에스디아이 주식회사 | 박막 트랜지스터의 제조 방법 |
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Publication number | Publication date |
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TW268133B (ko) | 1996-01-11 |
WO1994000882A1 (en) | 1994-01-06 |
US5508216A (en) | 1996-04-16 |
EP0602250A4 (en) | 1996-01-03 |
KR100309934B1 (ko) | 2002-06-20 |
DE69326123T2 (de) | 1999-12-23 |
EP0602250B1 (en) | 1999-08-25 |
DE69326123D1 (de) | 1999-09-30 |
US5757048A (en) | 1998-05-26 |
EP0602250A1 (en) | 1994-06-22 |
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