KR930014944A - 박막트랜지스터의 구조 - Google Patents

박막트랜지스터의 구조 Download PDF

Info

Publication number
KR930014944A
KR930014944A KR1019910025534A KR910025534A KR930014944A KR 930014944 A KR930014944 A KR 930014944A KR 1019910025534 A KR1019910025534 A KR 1019910025534A KR 910025534 A KR910025534 A KR 910025534A KR 930014944 A KR930014944 A KR 930014944A
Authority
KR
South Korea
Prior art keywords
semiconductor layer
source
gate
layer
drain
Prior art date
Application number
KR1019910025534A
Other languages
English (en)
Other versions
KR950003235B1 (ko
Inventor
소희섭
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019910025534A priority Critical patent/KR950003235B1/ko
Priority to JP34830592A priority patent/JP3401036B2/ja
Priority to US07/998,533 priority patent/US5347146A/en
Publication of KR930014944A publication Critical patent/KR930014944A/ko
Application granted granted Critical
Publication of KR950003235B1 publication Critical patent/KR950003235B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 LCD등에 응용되는 박막트랜지스터에 관한 것으로 소오스/드레인 접촉저항과 직렬저항을 작게하고 반도체층과 도핑층을 사용하여도 충분한 공정변수 오차 허용치를 가질 수 있는 구조 및 제조방법에 관한 것이다. 그 구조 및 제조방법은 절연기판위에 n형 반도체층과 금속층을 적층하고 패터닝하여 소오스/드레인영역을 형성하고 채널영역에 활성반도체층을 소오스/드레인 영역과 야간 겹치도록 형성하고 그 위에 절연막과 게이트를 형성한 것이다. 여기서 게이트를 오프셋되게 형성하여 활성반도체층중 소오스/드레인쪽에 P형 반도체층을 형성할 수도 있고, n형 반도체층과 금속층의 적층구조를 반대로 할 수도 있다. 따라서, 공정비용을 줄이고, 수율이 향상시킬 뿐만 아니라 전기적 신호특성을 향상시킬 수 있다.

Description

박막트랜지스터의 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 제1실시예 박막트랜지스터의 구조단면도,
제4도는 본 발명의 제2실시예 박막트랜지스터의 구조단면도,
제5도는 본 발명의 제3실시예 박막트랜지스터의 구조단면도,
제6도는 본 발명의 제4실시예 박막트랜지스터의 구조단면도,
제7도는 본 발명의 제5실시예 박막트랜지스터의 구조단면도,
제8도는 본 발명의 제6실시예 박막트랜지스터의 구조단면도,
제9도는 제5도의 박막트랜지스터의 제조공정 단면도.

Claims (6)

  1. 절연기판위에 제1도전형 반도체층과 금속층이 적층되어 소오스/드레인 영역이 형성되고 채널영역에는 상기 소오스/드레인 영역의 일측부분과 겹치도록 활성반도체층이 형성되고 전면이 게이트 절연막으로 격리되어 채널 영역에는 게이트가 형성되고 소오스/드레인영역은 콘텍이 형성되어 그 부위에 소오스/드레인 전극이 형성되어 이루어짐을 특징으로 하는 박막트랜지스터의 구조.
  2. 절연기판위에 제1도전형 반도체층과 금속층이 차례로 적층되어 CMOS의 소오스/드레인이 형성되고, 채널 영역에는 소오스/드레인 일측부분에 겹치도록 활성반도체층이 형성되고, 그위에 게이트절연막이 형성되고 게이트 절연막의 제1도전형 MOS 영역에는 게이트가 오버랩되게 형성되고 제2도전형 MOS 영역에는 소오스/드레인으로부터 수평방향으로 소정의 길이만큼 오프셋되게 게이트가 형성되고 상기 소정의 길이에 상응하는 활성반도체층에는 제2도전층 이온주입층이 형성됨을 특징으로 하는 박막트랜지스터의 구조.
  3. 제1항 소오스/드레인영역으로부터 수평방향으로 게이트전극이 겹치지 않게 소정의 길이(△L)만큼 떨어지게 형성하여 상기 소정의 길이에 상응하는 활성반도체층에 제2도전형 불순물이온주입으로 제2도전형 이온주입층을 형성함을 특징으로 하는 박막트랜지스터.
  4. 제1항 또는 제2항에 있어서, 금속층과 제1도전형 반도체층의 적층구조가 반대로 형성된 것으로 금속층중 활성반도체층과 겹치는 부위에 제1도전형 반도체층을 적층하여 소오스/드레인 영역을 형성함을 특징으로 하는 박막트랜지스터의 구조.
  5. 제1항 또는 제2항에 있어서, 활성반도체층은 비정질규소를 증착한 후 레이저 열처리하여 폴리실리콘으로 변화시켜 형성함을 특징으로 하는 박막트랜지스터의 구조.
  6. 제1항 또는 제2항에 있어서, 게이트 절연막은 LPCVD법 또는 ECR법으로 형성함을 특징으로 하는 박막트랜지스터의 구조.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910025534A 1991-12-30 1991-12-30 반도체 소자의 구조 KR950003235B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019910025534A KR950003235B1 (ko) 1991-12-30 1991-12-30 반도체 소자의 구조
JP34830592A JP3401036B2 (ja) 1991-12-30 1992-12-28 半導体素子の構造
US07/998,533 US5347146A (en) 1991-12-30 1992-12-30 Polysilicon thin film transistor of a liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910025534A KR950003235B1 (ko) 1991-12-30 1991-12-30 반도체 소자의 구조

Publications (2)

Publication Number Publication Date
KR930014944A true KR930014944A (ko) 1993-07-23
KR950003235B1 KR950003235B1 (ko) 1995-04-06

Family

ID=19327040

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910025534A KR950003235B1 (ko) 1991-12-30 1991-12-30 반도체 소자의 구조

Country Status (3)

Country Link
US (1) US5347146A (ko)
JP (1) JP3401036B2 (ko)
KR (1) KR950003235B1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06124913A (ja) * 1992-06-26 1994-05-06 Semiconductor Energy Lab Co Ltd レーザー処理方法
US7081938B1 (en) * 1993-12-03 2006-07-25 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
JP3864029B2 (ja) * 2000-03-24 2006-12-27 松下電器産業株式会社 半導体パッケージ及び半導体パッケージの製造方法
KR101293566B1 (ko) 2007-01-11 2013-08-06 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
JP2008311545A (ja) * 2007-06-18 2008-12-25 Hitachi Displays Ltd 表示装置
JP2009049080A (ja) * 2007-08-15 2009-03-05 Hitachi Displays Ltd 表示装置
JP4947152B2 (ja) 2007-12-05 2012-06-06 三菱電機株式会社 接触子装置
US8841661B2 (en) * 2009-02-25 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Staggered oxide semiconductor TFT semiconductor device and manufacturing method thereof
US8008691B2 (en) * 2009-07-21 2011-08-30 National Tsing Hua University Ion sensitive field effect transistor and production method thereof
CN112309969B (zh) * 2020-10-29 2022-10-18 厦门天马微电子有限公司 阵列基板的成型方法、阵列基板以及显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0824184B2 (ja) * 1984-11-15 1996-03-06 ソニー株式会社 薄膜トランジスタの製造方法
JPH0824103B2 (ja) * 1984-11-26 1996-03-06 ソニー株式会社 薄膜トランジスタの製造方法
JPH06101564B2 (ja) * 1985-02-27 1994-12-12 株式会社東芝 アモルフアスシリコン半導体装置
JP2779492B2 (ja) * 1985-09-26 1998-07-23 セイコーインスツルメンツ株式会社 薄膜トランジスタ装置とその製造方法
ATE77177T1 (de) * 1985-10-04 1992-06-15 Hosiden Corp Duennfilmtransistor und verfahren zu seiner herstellung.
US4851363A (en) * 1986-07-11 1989-07-25 General Motors Corporation Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses
JPS6347981A (ja) * 1986-08-18 1988-02-29 Alps Electric Co Ltd 薄膜トランジスタおよびその製造方法
US4849797A (en) * 1987-01-23 1989-07-18 Hosiden Electronics Co., Ltd. Thin film transistor
JPS63190385A (ja) * 1987-02-02 1988-08-05 Fujitsu Ltd 薄膜トランジスタ及びその製造方法
JPS6461061A (en) * 1987-09-01 1989-03-08 Fujitsu Ltd A-si thin film transistor
JPH01276671A (ja) * 1988-04-27 1989-11-07 Seikosha Co Ltd トップスタガー型非晶質シリコン薄膜トランジスタ
US4951113A (en) * 1988-11-07 1990-08-21 Xerox Corporation Simultaneously deposited thin film CMOS TFTs and their method of fabrication

Also Published As

Publication number Publication date
JPH0629319A (ja) 1994-02-04
US5347146A (en) 1994-09-13
JP3401036B2 (ja) 2003-04-28
KR950003235B1 (ko) 1995-04-06

Similar Documents

Publication Publication Date Title
KR100237279B1 (ko) Misfet, 상보형misfet 및 그 제조방법
KR940702312A (ko) 박막 트랜지스터, 고체장치, 표시장치 및, 박막 트랜지스터의 제조방법(Thin film transistor, solid device, display device and manufacturing mothed of a thin film transistor)
KR930011232A (ko) 불휘발성 반도체메모리장치 및 그 제조방법
KR940010367A (ko) 반도체장치 및 그 제조방법
KR840008537A (ko) 반도체장치
KR950021772A (ko) 적어도 하나의 모오스(mos) 트랜지스터를 구비한 집적회로의 제조방법
KR980005382A (ko) Soi소자 및 그 제조방법
KR920010975A (ko) 반도체장치 및 그의 제조방법
KR930014944A (ko) 박막트랜지스터의 구조
KR970009054B1 (ko) 평면구조 모스 트랜지스터 및 그 제조방법
KR920020725A (ko) 초고집적 반도체 메모리장치의 제조방법
JP2857900B2 (ja) 薄膜トランジスタの製造方法
JP2776820B2 (ja) 半導体装置の製造方法
KR970030676A (ko) 반도체 장치 및 그 제조 방법
KR0179066B1 (ko) 박막트랜지스터 및 그 제조방법
JPH0697694B2 (ja) 相補型薄膜トランジスタ
KR930009116A (ko) 박막트랜지스터와 그의 제조방법
JPH04364074A (ja) 絶縁ゲート電界効果トランジスタ
JP2020512683A (ja) 薄膜トランジスタアレイ基板、低温ポリシリコン薄膜トランジスタ、及び低温ポリシリコン薄膜トランジスタの製造方法
KR930017217A (ko) 박막 트랜지스터의 제조방법
JP2864499B2 (ja) 電界効果型薄膜トランジスタ
KR890004425B1 (ko) 채널 영역만을 고농도로 도우핑시킨 서브마이크론mosfet장치 및 그 제조방법
JPH04115538A (ja) 半導体装置
JPH0341479Y2 (ko)
KR980005890A (ko) 고전압 반도체 소자 및 그의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080401

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee