KR840008537A - 반도체장치 - Google Patents

반도체장치 Download PDF

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KR840008537A
KR840008537A KR1019840001637A KR840001637A KR840008537A KR 840008537 A KR840008537 A KR 840008537A KR 1019840001637 A KR1019840001637 A KR 1019840001637A KR 840001637 A KR840001637 A KR 840001637A KR 840008537 A KR840008537 A KR 840008537A
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source region
drain
field effect
effect transistor
semiconductor device
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KR1019840001637A
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KR910006249B1 (ko
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마사다라(외1) 호리우지
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미쓰다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
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Priority claimed from JP58121185A external-priority patent/JPS6014461A/ja
Application filed by 미쓰다 가쓰시게, 가부시기 가이샤 히다찌 세이사꾸쇼 filed Critical 미쓰다 가쓰시게
Publication of KR840008537A publication Critical patent/KR840008537A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

내용 없음.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도 내지 제5도는 본 발명의 제1의 실시예의 제조 공정을 공정순으로 도시한 단면도.

Claims (11)

  1. 전계 효과 트랜지스터에 있어서, 반도체 기판과 반대 도전형의 드레인 또는 소오스 영역에 있어서의 최대 불순물 농도가 1020㎝-3미만 내지 1018㎝-3이상에서 구성되고, 또, 상기 드레인 또는 소오스영역 표면의 적어도 일부는, 높은 융점 금속층, 또는 그 실리싸이드 층과 50㎚을 초과하지 않는 두께를 가진 높은 불순물 농도 영역으로 되는 높은 도전층과 접하고 있는 것을 특징으로 하는 반도체장치.
  2. 특허청구의 범위 제1항 기재의 전계 효과 트랜지스터에 있어서, 상기 높은 도전층이 고융점 금속층 또는 그 실리싸이드 층만으로 구성되어 있는 것을 특징으로 하는 반도체장치.
  3. 특허청구의 범위 제1항 기재의 전계효과 트랜지스터에 있어서, 상기 드레인 또는 소오스 영역의 적어도 일부가 게이트 전극 아래에 존재하는 것을 특징으로 하는 반도체장치.
  4. 특허청구의 범위 제1항 기재의 전계 효과 트랜지스터에 있어서, 상기 드레인 또는 소오스 영역의 적어도 한쪽이, 적어도 2회의 이온 주입에 의해서 형성되는 것을 특징으로 하는 반도체장치.
  5. 특허청구의 범위 제3항 기재의 전계 효과 트랜지스터에 있어서, 상기 게이트 전극이 Mo 박막, 또는 실리콘 박막으로 구성되는 것을 특징으로 하는 반도체장치.
  6. 특허청구의 범위 제3항 기재의 전계효과 트랜지스터에 있어서, 상기 게이트 전극 측벽부에 비유전률이 실리콘산화막 보다 높음 게이트 측벽 절연막을 형성하여 되는 것을 특징으로 하는 반도체장치.
  7. 특허청구의 범위 제6항 기재의 전계 효과 트랜지스터에 있어서, 상기 측벽 절연막을 실리콘 질화막으로 구성한 것을 특징으로 하는 반도체장치.
  8. 불순물 확산 영역의 최대 불순물 농도가 1018내지 1020㎝-3정도의 N형 드레인 또는 소오스 영역과 최대 불순물 농도가 1017내지 1019㎝-3정도의 P형 드레인 또는 소오스 영역을 가지며, 또 상기 각 드레인 또는 소오스 영역을 가지며, 또 상기 각 드레인 또는 소오스 영역의 적어도 일부가 높은 융점 금속 또는 해당 금속의 실리싸이드 층과 접합되여서 구성되고 있는 것을 특징으로 하는 반도체장치.
  9. 상기 각 드레인 또는 소오스 영역의 일부는, 반도체 기관표면 위에 절연막을 거쳐서, 구성된 게이트 전극과 해당 게이트 전극의 측벽에 형성된 절연막을 거쳐서, 인접해서 형성되는 것을 특징으로 하는 특허청구의 범위 제8항 기재의 반도체 장치.
  10. 상기 N형 드레인 또는 소오스 영역은, 고융점 금속 또는 그 실리싸이드 층 바로 아래의 불순물 석출영역과, 실리콘 박막 내부의 대략 균일한 분포의 영역과, 급준한 농도 분포 영역의 3개의 불순물 농도 분포 영역을 수직방향으로 갖고 있는 것을 특징으로 하는 특허청구의 범위 제8항 기재의 반도체장치.
  11. 상기 각 드레인 또는 소오스 영역의 일부는 다결정 박막 또는 비정질 박막으로 형성되는 것을 특징으로 하는 특허청구의 범위 제9항 기재의 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840001637A 1983-04-01 1984-03-29 반도체 장치 KR910006249B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP5507583A JPS59205759A (ja) 1983-04-01 1983-04-01 Ｍｉｓ型電界効果トランジスタ
JP55075 1983-04-01
JP58-55075 1983-04-01
JP58121185A JPS6014461A (ja) 1983-07-04 1983-07-04 相補型絶縁ゲート電界効果トランジスタの製造方法
JP121185 1983-07-04
JP58-121185 1983-07-04

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Publication Number Publication Date
KR840008537A true KR840008537A (ko) 1984-12-15
KR910006249B1 KR910006249B1 (ko) 1991-08-17

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US (1) US4769686A (ko)
EP (1) EP0123936B1 (ko)
KR (1) KR910006249B1 (ko)
DE (1) DE3476144D1 (ko)

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6153761A (ja) * 1984-08-24 1986-03-17 Hitachi Ltd 半導体装置
DE3677627D1 (de) * 1985-04-24 1991-04-04 Gen Electric Halbleiteranordnung mit isoliertem gate.
US4849802A (en) * 1986-01-21 1989-07-18 Ibm Corporation Thermally stable low resistance contact
US4978628A (en) * 1986-11-19 1990-12-18 Teledyne Industries, Inc. Drail-well/extension high voltage MOS transistor structure and method of fabrication
US4796082A (en) * 1987-03-16 1989-01-03 International Business Machines Corporation Thermally stable ohmic contact for gallium-arsenide
JP2609619B2 (ja) * 1987-08-25 1997-05-14 三菱電機株式会社 半導体装置
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4914500A (en) * 1987-12-04 1990-04-03 At&T Bell Laboratories Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices
IT1216476B (it) * 1988-02-29 1990-03-08 Sgs Thomson Microelectronics Processo per l'ottenimento di transitori a canale n per alta tensione, particolarmente per memorie eeprom con tecnologia cmos.
US5208472A (en) * 1988-05-13 1993-05-04 Industrial Technology Research Institute Double spacer salicide MOS device and method
JPH01298765A (ja) * 1988-05-27 1989-12-01 Fujitsu Ltd 半導体装置及びその製造方法
US5012100A (en) * 1988-06-08 1991-04-30 Siemens Aktiengesellschaft Method and apparatus for investigating the latch-up propagation in complementary-metal-oxide semiconductor (CMOS) circuits
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
US5063422A (en) * 1988-06-20 1991-11-05 At&T Bell Laboratories Devices having shallow junctions
US5270252A (en) * 1988-10-25 1993-12-14 United States Of America As Represented By The Secretary Of The Navy Method of forming platinum and platinum silicide schottky contacts on beta-silicon carbide
US5221853A (en) * 1989-01-06 1993-06-22 International Business Machines Corporation MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region
US4951100A (en) * 1989-07-03 1990-08-21 Motorola, Inc. Hot electron collector for a LDD transistor
US5258645A (en) * 1990-03-09 1993-11-02 Fujitsu Limited Semiconductor device having MOS transistor and a sidewall with a double insulator layer structure
US5283449A (en) * 1990-08-09 1994-02-01 Nec Corporation Semiconductor integrated circuit device including two types of MOSFETS having source/drain region different in sheet resistance from each other
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TW232751B (en) * 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
US5501989A (en) * 1993-03-22 1996-03-26 Semiconductor Energy Laboratory Co., Ltd. Method of making semiconductor device/circuit having at least partially crystallized semiconductor layer
US5539217A (en) * 1993-08-09 1996-07-23 Cree Research, Inc. Silicon carbide thyristor
US5439831A (en) * 1994-03-09 1995-08-08 Siemens Aktiengesellschaft Low junction leakage MOSFETs
JP2560637B2 (ja) * 1994-04-28 1996-12-04 日本電気株式会社 電界効果トランジスタ及びその製造方法
US5675167A (en) 1994-11-24 1997-10-07 Nippondenso Co., Ltd. Enhancement-type semiconductor having reduced leakage current
JPH09186324A (ja) * 1995-12-21 1997-07-15 Texas Instr Inc <Ti> ケイ化物化されたゲートおよび接触体を備えた電力用トランジスタ
US5897363A (en) * 1996-05-29 1999-04-27 Micron Technology, Inc. Shallow junction formation using multiple implant sources
US6236085B1 (en) 1996-11-11 2001-05-22 Denso Corporation Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate
US5793083A (en) * 1996-11-25 1998-08-11 Texas Instruments Incorporated Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity
US5844276A (en) * 1996-12-06 1998-12-01 Advanced Micro Devices, Inc. CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof
US5852306A (en) * 1997-01-29 1998-12-22 Micron Technology, Inc. Flash memory with nanocrystalline silicon film floating gate
JP4401448B2 (ja) * 1997-02-24 2010-01-20 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6838320B2 (en) * 2000-08-02 2005-01-04 Renesas Technology Corp. Method for manufacturing a semiconductor integrated circuit device
US6794255B1 (en) * 1997-07-29 2004-09-21 Micron Technology, Inc. Carburized silicon gate insulators for integrated circuits
US7196929B1 (en) 1997-07-29 2007-03-27 Micron Technology Inc Method for operating a memory device having an amorphous silicon carbide gate insulator
US5886368A (en) 1997-07-29 1999-03-23 Micron Technology, Inc. Transistor with silicon oxycarbide gate and methods of fabrication and use
US6965123B1 (en) 1997-07-29 2005-11-15 Micron Technology, Inc. Transistor with variable electron affinity gate and methods of fabrication and use
US7154153B1 (en) 1997-07-29 2006-12-26 Micron Technology, Inc. Memory device
US6936849B1 (en) 1997-07-29 2005-08-30 Micron Technology, Inc. Silicon carbide gate transistor
US6031263A (en) 1997-07-29 2000-02-29 Micron Technology, Inc. DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate
US6746893B1 (en) 1997-07-29 2004-06-08 Micron Technology, Inc. Transistor with variable electron affinity gate and methods of fabrication and use
US6417110B1 (en) * 1997-08-23 2002-07-09 Radiant Technologies Inc Method for constructing heat resistant electrode structures on silicon substrates
US6306712B1 (en) * 1997-12-05 2001-10-23 Texas Instruments Incorporated Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing
WO2000010198A1 (en) * 1998-08-11 2000-02-24 Koninklijke Philips Electronics N.V. Method of selectively forming silicide
US6878968B1 (en) * 1999-05-10 2005-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US6137126A (en) * 1999-08-17 2000-10-24 Advanced Micro Devices, Inc. Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer
JP2001119021A (ja) * 1999-10-20 2001-04-27 Nec Corp 半導体装置の製造方法
JP3833903B2 (ja) * 2000-07-11 2006-10-18 株式会社東芝 半導体装置の製造方法
JP4819215B2 (ja) * 2000-07-24 2011-11-24 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置およびその製造方法
KR100493206B1 (ko) * 2001-01-16 2005-06-03 가부시키가이샤 히타치세이사쿠쇼 반도체장치 및 그 제조방법
JP4676069B2 (ja) * 2001-02-07 2011-04-27 パナソニック株式会社 半導体装置の製造方法
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
JP4413779B2 (ja) * 2002-12-10 2010-02-10 株式会社半導体エネルギー研究所 発光装置およびその作製方法
JP4711595B2 (ja) * 2002-12-10 2011-06-29 株式会社半導体エネルギー研究所 Ｅｌディスプレイ及び電子機器
US7615822B1 (en) * 2002-12-23 2009-11-10 Volterra Semiconductor Corporation Diffused drain transistor
TWI253684B (en) * 2003-06-02 2006-04-21 Tokyo Electron Ltd Method and system for using ion implantation for treating a low-k dielectric film
US7220633B2 (en) * 2003-11-13 2007-05-22 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused MOSFET
US7074659B2 (en) * 2003-11-13 2006-07-11 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor
US7163856B2 (en) 2003-11-13 2007-01-16 Volterra Semiconductor Corporation Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor
US7081655B2 (en) * 2003-12-03 2006-07-25 Advanced Micro Devices, Inc. Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect
US7514762B2 (en) * 2003-12-15 2009-04-07 Koninklijke Philips Electronics N.V. Active matrix pixel device with photo sensor
US7504327B2 (en) * 2004-06-14 2009-03-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing thin film semiconductor device
US7745293B2 (en) 2004-06-14 2010-06-29 Semiconductor Energy Laboratory Co., Ltd Method for manufacturing a thin film transistor including forming impurity regions by diagonal doping
US7179696B2 (en) * 2004-09-17 2007-02-20 Texas Instruments Incorporated Phosphorus activated NMOS using SiC process
US7405443B1 (en) 2005-01-07 2008-07-29 Volterra Semiconductor Corporation Dual gate lateral double-diffused MOSFET (LDMOS) transistor
US8461628B2 (en) * 2005-03-18 2013-06-11 Kovio, Inc. MOS transistor with laser-patterned metal gate, and method for making the same
US7326609B2 (en) * 2005-05-06 2008-02-05 Chartered Semiconductor Manufacturing, Ltd. Semiconductor device and fabrication method
US8901699B2 (en) 2005-05-11 2014-12-02 Cree, Inc. Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection
US7767515B2 (en) * 2006-02-27 2010-08-03 Synopsys, Inc. Managing integrated circuit stress using stress adjustment trenches
TW200742087A (en) * 2006-03-14 2007-11-01 Koninkl Philips Electronics Nv Source and drain formation
KR100770536B1 (ko) * 2006-07-19 2007-10-25 동부일렉트로닉스 주식회사 고전압 반도체 소자 및 이의 제조 방법
JP2008192985A (ja) * 2007-02-07 2008-08-21 Seiko Instruments Inc 半導体装置、及び半導体装置の製造方法
US7691693B2 (en) * 2007-06-01 2010-04-06 Synopsys, Inc. Method for suppressing layout sensitivity of threshold voltage in a transistor array
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
US20090108408A1 (en) * 2007-10-29 2009-04-30 Synopsys, Inc. Method for Trapping Implant Damage in a Semiconductor Substrate
US9472423B2 (en) * 2007-10-30 2016-10-18 Synopsys, Inc. Method for suppressing lattice defects in a semiconductor substrate
JP5239548B2 (ja) * 2008-06-25 2013-07-17 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
JP4845937B2 (ja) * 2008-07-24 2011-12-28 株式会社東芝 スピンｍｏｓｆｅｔおよびこのスピンｍｏｓｆｅｔを用いたリコンフィギュラブル論理回路
US8120058B2 (en) * 2009-10-28 2012-02-21 International Business Machines Corporation High-drive current MOSFET
KR101990622B1 (ko) 2011-11-23 2019-06-18 아콘 테크놀로지스 인코포레이티드 계면 원자 단일층의 삽입에 의한 ⅳ족 반도체에 대한 금속 접점의 개선
US9390928B2 (en) * 2013-10-22 2016-07-12 Globalfoundries Inc. Anisotropic dielectric material gate spacer for a field effect transistor
US20160071791A1 (en) * 2014-09-09 2016-03-10 Globalfoundries Inc. Multimetal interlayer interconnects
US9966141B2 (en) * 2016-02-19 2018-05-08 Nscore, Inc. Nonvolatile memory cell employing hot carrier effect for data storage
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
WO2018094205A1 (en) 2016-11-18 2018-05-24 Acorn Technologies, Inc. Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3590471A (en) * 1969-02-04 1971-07-06 Bell Telephone Labor Inc Fabrication of insulated gate field-effect transistors involving ion implantation
US4005450A (en) * 1970-05-13 1977-01-25 Hitachi, Ltd. Insulated gate field effect transistor having drain region containing low impurity concentration layer
FR2130094B1 (ko) * 1971-03-16 1977-04-01 Ibm
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS
JPS55143068A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Insulated gate semiconductor device
US4384301A (en) * 1979-11-07 1983-05-17 Texas Instruments Incorporated High performance submicron metal-oxide-semiconductor field effect transistor device structure
US4339869A (en) * 1980-09-15 1982-07-20 General Electric Company Method of making low resistance contacts in semiconductor devices by ion induced silicides
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
JPS584924A (ja) * 1981-07-01 1983-01-12 Hitachi Ltd 半導体装置の電極形成方法

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