KR970024284A - T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법(Production Method for Ion-implanted MESFET Comprising Self-aligned Lightly Doped Drain Structure and T-gate) - Google Patents

T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법(Production Method for Ion-implanted MESFET Comprising Self-aligned Lightly Doped Drain Structure and T-gate) Download PDF

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KR970024284A
KR970024284A KR1019950036681A KR19950036681A KR970024284A KR 970024284 A KR970024284 A KR 970024284A KR 1019950036681 A KR1019950036681 A KR 1019950036681A KR 19950036681 A KR19950036681 A KR 19950036681A KR 970024284 A KR970024284 A KR 970024284A
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오응기
양전욱
박철순
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양승택
한국전자통신연구소
이준
한국전기통신공사
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Abstract

본 발명은 T형 게이트와 자기정렬 LDD 구조를 갖는 MESFET의 제조방법에 관한 것으로서, 양측에 소오스 및 드레인 영역이 형성된 채널영역의 소정 부분에 캡층을 이용하여 역메사부분을 형성하고, 상기 역메사부분을 마스크로 이용하여 소오스 및 드레인 영역과 채널 영역 사이에 작은 에너지와 저농도로 이온주입하여 소오스 쪽 보다 드레인 쪽이 넓은 저농도 소오스 및 드레인 영역을 형성하며, 상기 역메사부분의 표면이나 역메사부분을 제거하여 형성된 홈에 T형 게이트 전극을 저농도 소오스 및 드레인 영역과 접촉되지 않게 형성한다. 따라서, 저농도 드레인 영역이 넓으므로 드레인 항복 전압이 향상되며, T형 게이트 전극에 의해 게이트저항이 감소되므로 소자의 고주파특성 및 잡음특성을 향상시킬 수 있고, 게이트 전극과 저농도 소오스 및 드레인 영역이 접촉되는 것을 방지하므로 누설전류가 발생되는 것을 방지하며, 또한, 역메사부분 형성시 식각에 의한 채널층의 두께를 조절할 수 있으므로 게이트의 길이와 채널층의 두께의 비를 크게하여 숏채널 효과를 줄인다.

Description

T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법(Production Method for Ion-implanted MESFET Comprising Self-aligned Lightly Doped Drain Structure and T-gate)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도(A) 내지 (F)는 본 발명의 일 실시예에 따른 전계효과 트랜지스터의 단면도,
제 3 도(A) 내지 (C)는 본 발명의 다른 실시예에 따른 전계효과 트랜지스터의 단면도.

Claims (15)

  1. 반절연성 화합물 반도체 기판의 소정 부분에 소정 도전형의 채널영역을 형성하는 공정과, 상기 채널영역의 가운데 부분을 제외한 양측에 상기 채널영역과 동일한 도전형의 불순물을 고농도로 도핑된 소오스 및 드레인 영역을 형성하는 공정과, 상기 채널영역 상의 소정 부분에 캡층을 형성하고 이 캡층을 마스크로 이용하여 상기 반도체 기판의 노출된 부분을 습식식각하여 상기 채널영역 상에 상기 소오스영역 및 드레인 영역과 서로 다른 이격 거리를 갖는 역메사부분을 형성하는 공정과, 상기 캡층을 마스크로 이용하여 상기 채널영역과 상기 소오스 및 드레인 영역의 사이에 상기 소오스 및 드레인 영역과 동일한 도전형의 저농도 소오스 및 드레인 영역을 형성하는 공정과, 상기 캡층을 제거하고 상기 반도체 기판의 상부에 역메사부분의 표면이 노출되도록 보호막을 형성하는 공정과, 상기 소오스 및 드레인 영역이 노출되도록 보호막을 제거하고 소오스 및 드레인전극을 형성하는 공정과, 상기 역메사부분을 제거하여 채널영역의 소정 부분에 T형 게이트 전극을 형성하는 공정을 구비하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  2. 제 1 항에 있어서, 상기 채널영역을 이온주입 방법 또는 에피택셜방법으로 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조 방법.
  3. 제 2 항에 있어서, 상기 채널영역을 N형 또는 P형 도전형을 도핑하여 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  4. 제 3 항에 있어서, 상기 N형 불순물이 Si인 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  5. 제 3 항에 있어서, 상기 P형 불순물이 Be 또는 Mg인 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  6. 제 1 항에 있어서, 상기 캡층을 고융점금속, 상기 고융점금속의 화합물, 또는, 상기 고융점금속의 실리사이드로 형성하는 T형 게이트와 자기 정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  7. 제 6 항에 있어서, 상기 캡층을 스퍼터링 또는 진공증착 방법으로 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  8. 제 1 항에 있어서, 상기 역메사부분을 소오스영역 보다 드레인 영역의 이격 거리가 크도록 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  9. 제 8 항에 있어서, 상기 역메사부분을 H3PO4: H2O2: H2O가 4 : 1 : 50의 비율로 혼합된 용액으로 습식식각하여 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  10. 제 9 항에 있어서, 상기 역메사 부분을 ∼60° 의 각도로 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  11. 제 1 항에 있어서, 상기 역메사 형태의 반절연성 화합물 반도체 기판을 이용하여 보호막 이 역메사 형태의 열린 부분을 갖도록 하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  12. 제 11 항에 있어서, 상기 역메사 형태의 열린 부분을 갖는 보호막을 이용하여 미세선폭 게이트 패턴을 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  13. 반절연성 화합물 반도체 기판의 소정 부분에 소정 도전형의 채널영역을 형성하는 공정과, 상기 채널영역의 가운데 부분을 제외한 양측에 상기 채널영역과 동일한 도전형의 불순물을 고농도로 도핑된 소오스 및 드레인 영역을 형성하는 공정과, 상기 채널영역 상의 소정 부분에 게이트 전극을 형성하고 이 게이트 전극을 마스크로 이용하여 상기 반도체 기판의 노출된 부분을 습식식각하여 상기 채널영역 상에 상기 소오스영역 및 드레인 영역과 서로 다른 이격 거리를 갖는 역메사부분을 형성하는 공정과, 상기 게이트 전극을 마스크로 이용하여 상기 채널영역과 상기 소오스 및 드레인 영역의 사이에 상기 소오스 및 드레인 영역과 동일한 도전형의 저농도 소오스 및 드레인 영역을 형성하는 공정과, 상기 반도체 기판의 상부에 게이트 전극의 표면이 노출되도록 보호막을 형성하는 공정과, 상기 소오스 및 드레인 영역이 노출되도록 보호막을 제거하고 소오스 및 트래인전극을 형성하는 공정과, 상기 게이트 전극의 상부에 도전성 금속을 증착하여 T자형의 게이트 전극을 형성하는 공정을 구비하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  14. 제 13 항에 있어서, 상기 게이트 전극을 고융점금속, 상기 고융점금속의 화합물 또는 상기 고융점금속의 실리사이드로 형성하는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
  15. 제 13 항에 있어서, 상기 T형 게이트 전극 형성시 도전성금속이 상기 소오스 및 드레인 전극에도 증착되는 T형 게이트와 자기정렬 LDD 구조를 갖는 전계효과 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950036681A 1995-10-23 1995-10-23 T형 게이트와 자기정렬 ldd 구조를 갖는 전계효과 트랜지스터의 제조방법 KR0161201B1 (ko)

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KR1019950036681A KR0161201B1 (ko) 1995-10-23 1995-10-23 T형 게이트와 자기정렬 ldd 구조를 갖는 전계효과 트랜지스터의 제조방법
US08/566,709 US5580803A (en) 1995-10-23 1995-12-04 Production method for ion-implanted MESFET having self-aligned lightly doped drain structure and T-type gate
JP7316873A JP2901905B2 (ja) 1995-10-23 1995-12-05 Ｔ型ゲートと自己整列ｌｄｄ構造をもつ電界効果トランジスタの製造方法

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TW347561B (en) * 1997-06-20 1998-12-11 Ti Acer Co Ltd Method of forming a T-gate Lightly-Doped Drain semiconductor device
US6246096B1 (en) * 1998-06-24 2001-06-12 Advanced Micro Devices Totally self-aligned transistor with tungsten gate
US6458640B1 (en) * 2001-06-04 2002-10-01 Anadigics, Inc. GaAs MESFET having LDD and non-uniform P-well doping profiles
JP2003037264A (ja) 2001-07-24 2003-02-07 Toshiba Corp 半導体装置およびその製造方法
US20090275182A1 (en) * 2008-05-01 2009-11-05 International Business Machines Corporation Method for fabricating a metal high dielectric constant transistor with reverse-t gate
US7736981B2 (en) * 2008-05-01 2010-06-15 International Business Machines Corporation Metal high dielectric constant transistor with reverse-T gate
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US5185278A (en) * 1990-10-22 1993-02-09 Motorola, Inc. Method of making self-aligned gate providing improved breakdown voltage
US5182218A (en) * 1991-02-25 1993-01-26 Sumitomo Electric Industries, Ltd. Production methods for compound semiconductor device having lightly doped drain structure
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