JPS58142566A - 薄膜半導体装置 - Google Patents

薄膜半導体装置

Info

Publication number
JPS58142566A
JPS58142566A JP2555982A JP2555982A JPS58142566A JP S58142566 A JPS58142566 A JP S58142566A JP 2555982 A JP2555982 A JP 2555982A JP 2555982 A JP2555982 A JP 2555982A JP S58142566 A JPS58142566 A JP S58142566A
Authority
JP
Japan
Prior art keywords
thin film
poly
layer
semiconductor device
film semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2555982A
Other languages
English (en)
Inventor
Toshiaki Ogata
尾形　俊昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP2555982A priority Critical patent/JPS58142566A/ja
Publication of JPS58142566A publication Critical patent/JPS58142566A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は多結晶シリ；ン薄属半導体装置の接合の構造に
関する。
本発明の目的は多結晶シリコン＊＊中の接合特性を良（
してシツンジスタ特性を改善し、液晶表示パネルの製造
等に役立てる事にある。
多結晶シリコン薄膜半導体装置は単結晶シリコン薄族半
導体装置と比較して技術的に容易１ｃ瀘産に適しており
、またアモルファスシリコン薄膜半導体装置と比較して
移動度が大きい長所があるが熱拡散法もしくはイオン注
入法で形成した高濃度Ｍ型拡散層領域と薄膜基体である
真性半導体もしくは低鹸度Ｐ型半導体領域の間の接合特
性が悪い欠点がある。
本発明は熱拡散法もしくはイオン注入法で形成した高濃
度ｙｍ拡散層領域と薄膜基体である真性半導体もしくは
低濃度ＰＷ半導体領域の間にイオン注入法によって低濃
度のｘｍ拡散層を形成する事によって接合特性を改善す
るものである。
以下実施例によって騨しく説明する。
第１図は、本発明の構造を持つＭＯｌｉ［薄膜トランジ
スタの断面図で、ある、高ｆｌｋｌＩＮｔｌｉ拡散層１
．２と薄膜基体３の間にゲート配！１４に自己整合して
低濃度のＮ型拡散層５．６を形成する。ゲート配Ｉｉ！
ｉｉ４は多結晶シリコン、アルミニウム、高融点金ｊ４
．高融点金属シリサイドのいずれも使用できる。
嬉２図は本発明の構造を持つＭｏＳ型薄属トランジスタ
の他の例の断面図である０Ｍｍ不純物をゲート配ｌ１ｌ
Ｉ７に自己整合してイオン注入した後熱アニールによっ
て拡散して低１ＩＩＩＬ拡散層８，９を形成し、続いて
同じくゲート配線７に自己整合して高′ｆＩｋ度ｘｍ拡
散層１０．１１を形成する。第２図の例ではゲート配ｍ
７の材質は熱アニールに耐えられる多結晶シリコン、高
融点金属、高融点金属シリすイドに限られる。
＃Ｉ５図は本発明の構造を持つＭｏｌ臘薄膜Ｆランジス
タの特性１２を従来のＭＯＩｌｌ１ｍ１＃膜トランジス
タの特性１３の比較図であるｅ［から明らかな様に本発
明の構造を持つＭＯＩＩＩ）ツンジスタではゲートをオ
フにした状態でのリーク電流が従来のものに比べて一桁
ｉｉ度小さくなる。従って液晶表示パネルのスイッチン
グトランジスタアレイに使用した場合には従来のものよ
りｍ１ｌｌｉな表示効果が期待できる。
【図面の簡単な説明】
第１図、第２図は本発明の構造を持つＭＯＳ型）ランジ
スタの断ｌ１１ｗ１である。 第３図は本発明の構造を持つＭＯ８蓋トッンジスタと従
来のトランジスタの特性比較図である。 １．２，１０．１１・・・・・・高濃度ｘｍ拡散層５　
、６　、８　、９・・・・・・低濃度ＭＷ拡散層以上 出願人　株式金社諏訪精工舎

Claims (1)

    【特許請求の範囲】
  1. 高濃度ＭＷ牛導体領域と真性半導体もしくはＰ渥半導体
    領域の間に低濃度ＷＩｍ１半導体領域が形成された事を
    特徴とする多結晶シリコン薄膜半導体装置。
JP2555982A 1982-02-19 1982-02-19 薄膜半導体装置 Pending JPS58142566A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2555982A JPS58142566A (ja) 1982-02-19 1982-02-19 薄膜半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2555982A JPS58142566A (ja) 1982-02-19 1982-02-19 薄膜半導体装置

Publications (1)

Publication Number Publication Date
JPS58142566A true JPS58142566A (ja) 1983-08-24

Family

ID=12169291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2555982A Pending JPS58142566A (ja) 1982-02-19 1982-02-19 薄膜半導体装置

Country Status (1)

Country Link
JP (1) JPS58142566A (ja)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60251667A (ja) * 1984-05-28 1985-12-12 Seiko Epson Corp 薄膜トランジスタ−
JPS61104671A (ja) * 1984-10-29 1986-05-22 Sharp Corp 電界効果トランジスタ
JPS63204769A (ja) * 1987-02-20 1988-08-24 Nippon Telegr & Teleph Corp <Ntt> 薄膜トランジスタの製造方法
JPH01187977A (ja) * 1988-01-22 1989-07-27 Nec Corp 絶縁ゲート電界効果トランジスタおよびその製造方法
JPH0234970A (ja) * 1988-07-25 1990-02-05 Sony Corp 電界効果型薄膜トランジスタ
JPH04188633A (ja) * 1990-11-19 1992-07-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0479424U (ja) * 1990-11-23 1992-07-10
WO1994000882A1 (en) 1992-06-24 1994-01-06 Seiko Epson Corporation Thin film transistor, solid-state device, display device, and method for manufacturing thin film transistor
US5323042A (en) * 1991-11-25 1994-06-21 Casio Computer Co., Ltd. Active matrix liquid crystal display having a peripheral driving circuit element
JPH07169974A (ja) * 1993-09-20 1995-07-04 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JPH07169975A (ja) * 1993-09-20 1995-07-04 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JPH09107110A (ja) * 1996-09-13 1997-04-22 Sony Corp Ｓｏｉｍｏｓトランジスタの製造方法
US6049092A (en) * 1993-09-20 2000-04-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6331723B1 (en) 1991-08-26 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device having at least two transistors having LDD region in one pixel
US6507069B1 (en) 1994-07-14 2003-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacture thereof
US6906383B1 (en) 1994-07-14 2005-06-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacture thereof
JP2010098321A (ja) * 1993-09-20 2010-04-30 Semiconductor Energy Lab Co Ltd 半導体装置

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60251667A (ja) * 1984-05-28 1985-12-12 Seiko Epson Corp 薄膜トランジスタ−
JPS61104671A (ja) * 1984-10-29 1986-05-22 Sharp Corp 電界効果トランジスタ
JPS63204769A (ja) * 1987-02-20 1988-08-24 Nippon Telegr & Teleph Corp <Ntt> 薄膜トランジスタの製造方法
JPH01187977A (ja) * 1988-01-22 1989-07-27 Nec Corp 絶縁ゲート電界効果トランジスタおよびその製造方法
JPH0234970A (ja) * 1988-07-25 1990-02-05 Sony Corp 電界効果型薄膜トランジスタ
JPH04188633A (ja) * 1990-11-19 1992-07-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0479424U (ja) * 1990-11-23 1992-07-10
US6803600B2 (en) 1991-08-26 2004-10-12 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US7821011B2 (en) 1991-08-26 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US7456427B2 (en) 1991-08-26 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US6331723B1 (en) 1991-08-26 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device having at least two transistors having LDD region in one pixel
US5323042A (en) * 1991-11-25 1994-06-21 Casio Computer Co., Ltd. Active matrix liquid crystal display having a peripheral driving circuit element
US5508216A (en) * 1992-06-24 1996-04-16 Seiko Epson Corporation Thin film transistor, solid device, display device and manufacturing method of a thin film transistor
KR100309934B1 (ko) * 1992-06-24 2002-06-20 구사마 사부로 박막트랜지스터,고체장치,표시장치,및박막트랜지스터의제조방법
US5757048A (en) * 1992-06-24 1998-05-26 Seiko Epson Corporation Thin film transistor, solid state device, display device and manufacturing method of a thin film transistor
WO1994000882A1 (en) 1992-06-24 1994-01-06 Seiko Epson Corporation Thin film transistor, solid-state device, display device, and method for manufacturing thin film transistor
US6049092A (en) * 1993-09-20 2000-04-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JPH07169975A (ja) * 1993-09-20 1995-07-04 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4675433B2 (ja) * 1993-09-20 2011-04-20 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4657361B2 (ja) * 1993-09-20 2011-03-23 株式会社半導体エネルギー研究所 半導体装置
US6867431B2 (en) * 1993-09-20 2005-03-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP2011035430A (ja) * 1993-09-20 2011-02-17 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JPH07169974A (ja) * 1993-09-20 1995-07-04 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2010098321A (ja) * 1993-09-20 2010-04-30 Semiconductor Energy Lab Co Ltd 半導体装置
US7635895B2 (en) 1994-07-14 2009-12-22 Semiconductor Energy Laboratory Co., Ltd. Display device
US6507069B1 (en) 1994-07-14 2003-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacture thereof
US7183614B2 (en) 1994-07-14 2007-02-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacture thereof
US6906383B1 (en) 1994-07-14 2005-06-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacture thereof
US6773971B1 (en) 1994-07-14 2004-08-10 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having lightly-doped drain (LDD) regions
US8273613B2 (en) 1994-07-14 2012-09-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacture thereof
JPH09107110A (ja) * 1996-09-13 1997-04-22 Sony Corp Ｓｏｉｍｏｓトランジスタの製造方法

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