KR920003644A - 마스터슬레이브형 플립플롭회로 - Google Patents

마스터슬레이브형 플립플롭회로 Download PDF

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Publication number
KR920003644A
KR920003644A KR1019910012174A KR910012174A KR920003644A KR 920003644 A KR920003644 A KR 920003644A KR 1019910012174 A KR1019910012174 A KR 1019910012174A KR 910012174 A KR910012174 A KR 910012174A KR 920003644 A KR920003644 A KR 920003644A
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KR
South Korea
Prior art keywords
transfer gates
inverters
supplied
input
inverted
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KR1019910012174A
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English (en)
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KR0170410B1 (ko
Inventor
지아끼 다까노
Original Assignee
오가 노리오
소니 가부시기가이샤
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Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920003644A publication Critical patent/KR920003644A/ko
Application granted granted Critical
Publication of KR0170410B1 publication Critical patent/KR0170410B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type

Landscapes

  • Logic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

내용 없음

Description

마스터슬레이브형 플립플롭회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 마스터슬레이브형 플립플롭회로의 기본구성을 나타낸 회로도,
제2도는 본원 발명의 데이터유지부를 나타낸 회로도,
제3도 A 내지 제3도 E는 본원 발명의 동작설명을 위한 타이밍차트.

Claims (2)

  1. 입력펄스신호 및 반전입력펄스신호가 데이터입력단자 및 반전데이터입력단자에 각각 공급되는 동시에 클록신호가 클록입력단자에 공급되는 제1, 제2전송게이트와, 제1, 제2인버터 및 이 제1, 제2인버터의 입출력단자 사이에 각각 교차접속된 제1, 제2저항기를 가지는 동시에 상기 제1, 제2전송게이트의 출력이 각각 공급되는 제1데이터유지부와, 상기 제1데이터유지부의 출력 및 반전클록입력 단자의 반전클록신호가 각각 공급되는 제3, 제4전송게이트와, 제3, 제4인버터 및 이 제3, 제4인버터의 입출력단자 사이에 각각 교차접속된 제3, 제4저항기를 가지는 동시에 상기 제3, 제4전송게이트의 출력이 각각 공급되는 제2데이터유지부를 구비한 것을 특징으로 하는 마스터슬레이브형 플립플롭회로.
  2. 제1항에 있어서, 상기 제1 내지 제4의 전송게이트의 소자 및 상기 제1 내지 제4인버터의 소자를 각각 GaAsFET로 구성하는 동시에 상기 제1 내지 제4저항기와 병렬로 제1 내지 제4콘덴서를 각각 접속한 것을 특징으로 하는 마스터슬레이브형 플립플롭회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910012174A 1990-07-18 1991-07-16 마스터슬레이브형 플립플롭회로 KR0170410B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-188100 1990-07-18
JP2188100A JPH0478215A (ja) 1990-07-18 1990-07-18 マスタースレーブ型フリップフロップ回路

Publications (2)

Publication Number Publication Date
KR920003644A true KR920003644A (ko) 1992-02-29
KR0170410B1 KR0170410B1 (ko) 1999-03-30

Family

ID=16217704

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910012174A KR0170410B1 (ko) 1990-07-18 1991-07-16 마스터슬레이브형 플립플롭회로

Country Status (5)

Country Link
US (1) US5140179A (ko)
EP (1) EP0467273B1 (ko)
JP (1) JPH0478215A (ko)
KR (1) KR0170410B1 (ko)
DE (1) DE69122189T2 (ko)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357153A (en) * 1993-01-28 1994-10-18 Xilinx, Inc. Macrocell with product-term cascade and improved flip flop utilization
US5406147A (en) * 1993-06-18 1995-04-11 Digital Equipment Corporation Propagation speedup by use of complementary resolver outputs in a system bus receiver
US5654653A (en) * 1993-06-18 1997-08-05 Digital Equipment Corporation Reduced system bus receiver setup time by latching unamplified bus voltage
US5391935A (en) * 1993-07-22 1995-02-21 International Business Machines Corporation Assertive latching flip-flop
US5532634A (en) * 1993-11-10 1996-07-02 Kabushiki Kaisha Toshiba High-integration J-K flip-flop circuit
EP0687071A1 (fr) * 1994-06-08 1995-12-13 Laboratoires D'electronique Philips S.A.S. Dispositif incluant un circuit à étages logiques dynamiques
US5508648A (en) * 1994-08-01 1996-04-16 Intel Corporation Differential latch circuit
GB2292855A (en) * 1994-08-31 1996-03-06 Texas Instruments Ltd CMOS latch suitable for low voltage operation
US5486777A (en) * 1994-09-07 1996-01-23 National Semiconductor Corporation Low power differential receiver input circuit
JP3043241B2 (ja) * 1994-10-24 2000-05-22 沖電気工業株式会社 可変遅延回路
US5684422A (en) * 1995-01-25 1997-11-04 Advanced Micro Devices, Inc. Pipelined microprocessor including a high speed single-clock latch circuit
US5672991A (en) * 1995-04-14 1997-09-30 International Business Machines Corporation Differential delay line circuit for outputting signal with equal pulse widths
JPH0955651A (ja) * 1995-08-15 1997-02-25 Toshiba Corp 論理回路
US6563356B2 (en) * 1999-10-19 2003-05-13 Honeywell International Inc. Flip-flop with transmission gate in master latch
US6417711B2 (en) 1999-10-19 2002-07-09 Honeywell Inc. High speed latch and flip-flop
AUPR223000A0 (en) * 2000-12-21 2001-01-25 Luminis Pty Limited A level sensitive latch
US7173475B1 (en) * 2003-03-26 2007-02-06 Cypress Semiconductor Corp. Signal transmission amplifier circuit
US7323911B2 (en) * 2005-11-21 2008-01-29 Macronix International Co., Ltd. Differential sense amplifier circuit and method triggered by a clock signal through a switch circuit
US7411432B1 (en) * 2006-07-31 2008-08-12 Lattice Semiconductor Corporation Integrated circuits and complementary CMOS circuits for frequency dividers
JP4954639B2 (ja) * 2006-08-25 2012-06-20 パナソニック株式会社 ラッチ回路及びこれを備えた半導体集積回路
US7764086B2 (en) * 2006-12-22 2010-07-27 Industrial Technology Research Institute Buffer circuit
CN101241247B (zh) * 2007-02-09 2010-05-26 群康科技(深圳)有限公司 移位寄存器及液晶显示装置
JP2009211732A (ja) * 2008-02-29 2009-09-17 Eastman Kodak Co シフトレジスタ回路および表示装置
US8725786B2 (en) * 2009-04-29 2014-05-13 University Of Massachusetts Approximate SRT division method
KR101340248B1 (ko) * 2010-05-31 2013-12-10 한국전자통신연구원 고속 플립플롭 회로 및 그 구성 방법
JP6056632B2 (ja) * 2013-04-22 2017-01-11 富士通株式会社 データ保持回路、及び、半導体集積回路装置
EP3001562B1 (en) * 2014-09-23 2021-09-01 Nxp B.V. Fault resistant flip-flop
CN117413463A (zh) * 2021-06-03 2024-01-16 新思科技有限公司 D型完全不同的高速静态置位-复位触发器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3042815A (en) * 1960-06-27 1962-07-03 Burroughs Corp High-speed, non-saturating transistor steering flip-flop
US3573509A (en) * 1968-09-09 1971-04-06 Texas Instruments Inc Device for reducing bipolar effects in mos integrated circuits
SE383325B (sv) * 1974-01-31 1976-03-08 Stella Maskiners Forseljnings Anordning vid ett hoj- och senkbart lyftorgan till lastfordon sasom truckar o.d. for fasthallning ovanifran av en av lyftorganet uppburen last
JPS55140321A (en) * 1979-04-18 1980-11-01 Nippon Hamondo Kk T-type flip flop
JPS57206072A (en) * 1981-06-12 1982-12-17 Hitachi Ltd Semiconductor device
JPS6010810A (ja) * 1983-06-29 1985-01-21 Fujitsu Ltd マスタ・スレ−ブ形フリツプフロツプ回路
EP0144654A3 (en) * 1983-11-03 1987-10-07 General Electric Company Semiconductor device structure including a dielectrically-isolated insulated-gate transistor
JPS61252707A (ja) * 1985-05-02 1986-11-10 Hitachi Ltd ラツチ回路
JPS61269412A (ja) * 1985-05-23 1986-11-28 Seiko Epson Corp Ｄ型ラツチ半導体集積回路
JPH0682840B2 (ja) * 1985-09-25 1994-10-19 日本電信電話株式会社 Ｍｏｓ形半導体装置
JPS6450568A (en) * 1987-08-21 1989-02-27 Mitsubishi Electric Corp Semiconductor device
JPH0234018A (ja) * 1988-07-25 1990-02-05 Oki Electric Ind Co Ltd フリップフロップ回路
US4939384A (en) * 1988-10-03 1990-07-03 Oki Electric Industry Co., Ltd Flip-flop circuit
JP2510710B2 (ja) * 1988-12-13 1996-06-26 三菱電機株式会社 絶縁体基板上の半導体層に形成されたｍｏｓ型電界効果トランジスタ

Also Published As

Publication number Publication date
JPH0478215A (ja) 1992-03-12
KR0170410B1 (ko) 1999-03-30
EP0467273A3 (en) 1992-04-22
EP0467273A2 (en) 1992-01-22
DE69122189T2 (de) 1997-04-17
US5140179A (en) 1992-08-18
DE69122189D1 (de) 1996-10-24
EP0467273B1 (en) 1996-09-18

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