JPS55140321A - T-type flip flop - Google Patents

T-type flip flop

Info

Publication number
JPS55140321A
JPS55140321A JP4823479A JP4823479A JPS55140321A JP S55140321 A JPS55140321 A JP S55140321A JP 4823479 A JP4823479 A JP 4823479A JP 4823479 A JP4823479 A JP 4823479A JP S55140321 A JPS55140321 A JP S55140321A
Authority
JP
Japan
Prior art keywords
input
diode
resistance
time constant
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4823479A
Other languages
Japanese (ja)
Inventor
Hiroyuki Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON HAMONDO KK
Original Assignee
NIPPON HAMONDO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON HAMONDO KK filed Critical NIPPON HAMONDO KK
Priority to JP4823479A priority Critical patent/JPS55140321A/en
Publication of JPS55140321A publication Critical patent/JPS55140321A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To prevent malfunctions caused by differential pulsatile noise and so on included in the trigger pulse signal, by integrating and inputting trigger pulses. CONSTITUTION:Integration time constant forming resistance R1 and the cathode of input trigger pulse stopping diode D1 are connected to one input of NAND gate N1, and output logic holding resistance R4 connected in parallel to the anode of diode D1 and one end of integration time constant forming capacitor C2 are connected to the other input, and the other end of C2 is connected to output Q' of NAND gate N2. Symmetrically to these connections, resistance R2 and the cathode of diode D2 are connected to one input of gate N2, and resistance R4 connected in parallel to the anode of diode D2 and one end of capacitor C2 are connected to the other input, and the other end of C2 is connected to output Q of gate N1. Then, the input logical value of trigger pulses is integrated; and when this value exceeds the threshold voltage, this circuit is operated. Since this circuit is not operated by a pulse shorter than time constant R1C2 or R2C2, the FF can be prevented from malfunctions even if differential noise is included in input pulses.
JP4823479A 1979-04-18 1979-04-18 T-type flip flop Pending JPS55140321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4823479A JPS55140321A (en) 1979-04-18 1979-04-18 T-type flip flop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4823479A JPS55140321A (en) 1979-04-18 1979-04-18 T-type flip flop

Publications (1)

Publication Number Publication Date
JPS55140321A true JPS55140321A (en) 1980-11-01

Family

ID=12797744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4823479A Pending JPS55140321A (en) 1979-04-18 1979-04-18 T-type flip flop

Country Status (1)

Country Link
JP (1) JPS55140321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0467273A2 (en) * 1990-07-18 1992-01-22 Sony Corporation Master-slave type flip-flop circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152767A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Process accomodation control method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152767A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Process accomodation control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0467273A2 (en) * 1990-07-18 1992-01-22 Sony Corporation Master-slave type flip-flop circuit
US5140179A (en) * 1990-07-18 1992-08-18 Sony Corporation Master-slave type flip-flop circuit

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