JPS5764394A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5764394A
JPS5764394A JP55136994A JP13699480A JPS5764394A JP S5764394 A JPS5764394 A JP S5764394A JP 55136994 A JP55136994 A JP 55136994A JP 13699480 A JP13699480 A JP 13699480A JP S5764394 A JPS5764394 A JP S5764394A
Authority
JP
Japan
Prior art keywords
level
circuit
resistance
data
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55136994A
Other languages
Japanese (ja)
Inventor
Tadanobu Nikaido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55136994A priority Critical patent/JPS5764394A/en
Publication of JPS5764394A publication Critical patent/JPS5764394A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Abstract

PURPOSE:To exactly execute an operation of a memory circuit, by inserting resistances in series relation to the input sides of gates of two memory circuits constituting a semiconductor memory device having a D-type flip-flop function. CONSTITUTION:This device is constituted by inserting a resistance 51, a resistance 52 ann a resistance 53 in series relation between an input data inputted gate 3 of a memory circuit M1 and an input data line A, to the input side of a gate of a memory circuit M2 in the same way and to the input side of a positive feedback gate 7, respectively, by which in case when a data of the memory circuit M2 is in ''H'' level, the potential of an output point of a logical circuit (inverter) 5 of the circuit M1 exceeds a logical threshold level of a circuit 5, and even if a clock pulse is delayed against a reference clock pulse phi and -phi, such a malfunction as a data of the circuit M1 is varied to ''L'' level from ''H'' level does not occur, and also in case when a data of the circuits M1, M2 is in ''M'' level, such a malfunction as its ''H'' level is varied to ''L'' level does not occur in the same way, by the resistance 51.
JP55136994A 1980-10-01 1980-10-01 Semiconductor memory device Pending JPS5764394A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55136994A JPS5764394A (en) 1980-10-01 1980-10-01 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55136994A JPS5764394A (en) 1980-10-01 1980-10-01 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5764394A true JPS5764394A (en) 1982-04-19

Family

ID=15188295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55136994A Pending JPS5764394A (en) 1980-10-01 1980-10-01 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5764394A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0219846A2 (en) * 1985-10-21 1987-04-29 Mitsubishi Denki Kabushiki Kaisha Latch circuit tolerant of undefined control signals
JPH04214299A (en) * 1990-12-10 1992-08-05 Mitsubishi Electric Corp Shift register
JP2011090761A (en) * 2009-09-24 2011-05-06 Semiconductor Energy Lab Co Ltd Drive circuit, display device provided with drive circuit, and electronic equipment provided with display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0219846A2 (en) * 1985-10-21 1987-04-29 Mitsubishi Denki Kabushiki Kaisha Latch circuit tolerant of undefined control signals
JPH04214299A (en) * 1990-12-10 1992-08-05 Mitsubishi Electric Corp Shift register
JP2011090761A (en) * 2009-09-24 2011-05-06 Semiconductor Energy Lab Co Ltd Drive circuit, display device provided with drive circuit, and electronic equipment provided with display device
JP2013148910A (en) * 2009-09-24 2013-08-01 Semiconductor Energy Lab Co Ltd Drive circuit
US9406398B2 (en) 2009-09-24 2016-08-02 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device including the driver circuit, and electronic appliance including the display device
US9991890B2 (en) 2009-09-24 2018-06-05 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device including the driver circuit, and electronic appliance including the display device

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