JPS5673921A - Chattering rejection circuit - Google Patents

Chattering rejection circuit

Info

Publication number
JPS5673921A
JPS5673921A JP15086879A JP15086879A JPS5673921A JP S5673921 A JPS5673921 A JP S5673921A JP 15086879 A JP15086879 A JP 15086879A JP 15086879 A JP15086879 A JP 15086879A JP S5673921 A JPS5673921 A JP S5673921A
Authority
JP
Japan
Prior art keywords
chattering
terminal
inverter
input
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15086879A
Other languages
Japanese (ja)
Other versions
JPS592206B2 (en
Inventor
Hiroshi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP54150868A priority Critical patent/JPS592206B2/en
Publication of JPS5673921A publication Critical patent/JPS5673921A/en
Publication of JPS592206B2 publication Critical patent/JPS592206B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Abstract

PURPOSE:To ensure to reject the chattering pulse, by controlling the input level of a C<->MOS inverter when the input signal level is inverted and holding said input level to one of the two levels when the input and output levels are corresponded. CONSTITUTION:When a terminal P is inverted to ''1'' with chattering, FETs T2, T3 are respectively on and off. Thus, the charge of a capacitor C is discharged via a resistor R. The time constant by the capacitor C and the resistor R can be set so that the potential at the terminal (a) reaches the threshold level V of an inverter V1 after the time (t) with this discharge. Accordingly, even if the pulse having narrower width than that of the time (t) by chattering is incoming, the voltage at the terminal (a) does not reach voltage V and the output of the inverter V1 is held at ''0''.
JP54150868A 1979-11-21 1979-11-21 Chattering removal circuit Expired JPS592206B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54150868A JPS592206B2 (en) 1979-11-21 1979-11-21 Chattering removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54150868A JPS592206B2 (en) 1979-11-21 1979-11-21 Chattering removal circuit

Publications (2)

Publication Number Publication Date
JPS5673921A true JPS5673921A (en) 1981-06-19
JPS592206B2 JPS592206B2 (en) 1984-01-17

Family

ID=15506128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54150868A Expired JPS592206B2 (en) 1979-11-21 1979-11-21 Chattering removal circuit

Country Status (1)

Country Link
JP (1) JPS592206B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0251275A2 (en) * 1986-07-02 1988-01-07 Kabushiki Kaisha Toshiba Noise cancelling circuit
US5990716A (en) * 1996-06-27 1999-11-23 Lsi Logic Corporation Method and system for recovering digital data from a transmitted balanced signal
JP2008288809A (en) * 2007-05-16 2008-11-27 Fuji Electric Device Technology Co Ltd Noise elimination circuit, signal transmission circuit using isolation transformer, and power converter

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6121301U (en) * 1984-02-13 1986-02-07 月星化成株式会社 insoles for shoes
JPS61128905A (en) * 1984-11-27 1986-06-17 株式会社アサヒコーポレーション Athletic shoe sole

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0251275A2 (en) * 1986-07-02 1988-01-07 Kabushiki Kaisha Toshiba Noise cancelling circuit
US5990716A (en) * 1996-06-27 1999-11-23 Lsi Logic Corporation Method and system for recovering digital data from a transmitted balanced signal
JP2008288809A (en) * 2007-05-16 2008-11-27 Fuji Electric Device Technology Co Ltd Noise elimination circuit, signal transmission circuit using isolation transformer, and power converter

Also Published As

Publication number Publication date
JPS592206B2 (en) 1984-01-17

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