KR910005383A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

Info

Publication number
KR910005383A
KR910005383A KR1019900013288A KR900013288A KR910005383A KR 910005383 A KR910005383 A KR 910005383A KR 1019900013288 A KR1019900013288 A KR 1019900013288A KR 900013288 A KR900013288 A KR 900013288A KR 910005383 A KR910005383 A KR 910005383A
Authority
KR
South Korea
Prior art keywords
layer
crystal silicon
silicon layer
connection hole
semiconductor device
Prior art date
Application number
KR1019900013288A
Other languages
English (en)
Other versions
KR940000827B1 (ko
Inventor
슈이치 사마타
요시아키 마츠시타
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910005383A publication Critical patent/KR910005383A/ko
Application granted granted Critical
Publication of KR940000827B1 publication Critical patent/KR940000827B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/164—Three dimensional processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 반도체장치를 나타낸 단면도.

Claims (5)

  1. 반도체기판(11)과, 이 반도체기판(11)의 표면영역에 형성되는 확산층(12), 이 확산층(12)상에 접속구멍(14)을 형성하기 위해 상기 반도체기판(11)상에 형성되는 절연층(13), 상기 접속구멍(14)내의 상기 확산층(12)상에 형성되는 단결정실리콘층(15a), 상기 접속구멍(14)이 매립되도록 상기 단결정실리콘층(15a)상에 형성되는 비단결정실리콘층(15b) 및 이 비단결정실리콘층(15b)상에 형성되는 배선층(16)이 구비된 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 비단결정실리콘층(15b)이 다결정실리콘층인 것을 특징으로 하는 반도체장치.
  3. 제1항 또는 제2항에 있어서, 상기 단결정실리콘층(15a)은 그 막두께가 0.3㎛이하인 것을 특징으로 하는 반도체장치.
  4. 제2항에 있어서, 상기 단결정실리콘층(15a)에 발생하는 파셋트의 깊이는 상기 다결정실리콘층(15a)의 평균결정입경이한인 것을 특징으로 하는 반도체장치.
  5. 반도체기판(11)의 표면영역에 확산층(12)을 형성하는 공정과, 이 확산층(12)을 포함하는 상기 반도체기판(11)상에 절연층(13)을 형성하는 공정, 이 절연층(13)에 상기 확산층(12)에 이르는 접속구멍(14)을 형성하는 공정, 실리콘선택성장기술을 이용하여 상기 접속구멍(14)에 단결정실리콘층(15a)을 선택성장시킨 후, 이어서 상기 접속구멍(14)에 비단결정실리콘층(15b)을 선택성장시켜 이들 단결정실리콘층 (15a) 및 비단결정실리콘층(15b)에 의해 상기 접속구멍(14)을 매립하는 공정 및, 상기 비단결정실리콘층(15b)상에 절연층(16)을 형성하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900013288A 1989-08-29 1990-08-28 반도체장치 및 그 제조방법 KR940000827B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-222678 1989-08-29
JP1222678A JPH0671073B2 (ja) 1989-08-29 1989-08-29 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR910005383A true KR910005383A (ko) 1991-03-30
KR940000827B1 KR940000827B1 (ko) 1994-02-02

Family

ID=16786211

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900013288A KR940000827B1 (ko) 1989-08-29 1990-08-28 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (2) US5057899A (ko)
EP (1) EP0415537B1 (ko)
JP (1) JPH0671073B2 (ko)
KR (1) KR940000827B1 (ko)
DE (1) DE69031753T2 (ko)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629218A (en) * 1989-12-19 1997-05-13 Texas Instruments Incorporated Method for forming a field-effect transistor including a mask body and source/drain contacts
KR940006689B1 (ko) * 1991-10-21 1994-07-25 삼성전자 주식회사 반도체장치의 접촉창 형성방법
US5635411A (en) * 1991-11-12 1997-06-03 Rohm Co., Ltd. Method of making semiconductor apparatus
US5266517A (en) * 1991-12-17 1993-11-30 Texas Instruments Incorporated Method for forming a sealed interface on a semiconductor device
US5347161A (en) * 1992-09-02 1994-09-13 National Science Council Stacked-layer structure polysilicon emitter contacted p-n junction diode
US5557131A (en) * 1992-10-19 1996-09-17 At&T Global Information Solutions Company Elevated emitter for double poly BICMOS devices
US5639688A (en) * 1993-05-21 1997-06-17 Harris Corporation Method of making integrated circuit structure with narrow line widths
JPH07193024A (ja) * 1993-12-27 1995-07-28 Nec Corp 半導体装置およびその製造方法
KR950025908A (ko) * 1994-02-03 1995-09-18 김주용 반도체소자 제조방법
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
JP2964925B2 (ja) * 1994-10-12 1999-10-18 日本電気株式会社 相補型ｍｉｓ型ｆｅｔの製造方法
US5637518A (en) * 1995-10-16 1997-06-10 Micron Technology, Inc. Method of making a field effect transistor having an elevated source and an elevated drain
US5753555A (en) * 1995-11-22 1998-05-19 Nec Corporation Method for forming semiconductor device
US5885761A (en) * 1997-01-08 1999-03-23 Advanced Micro Devices Semiconductor device having an elevated active region formed from a thick polysilicon layer and method of manufacture thereof
US5872038A (en) * 1997-01-08 1999-02-16 Advanced Micro Devices Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof
WO1999004427A1 (de) 1997-07-15 1999-01-28 Infineon Technologies Ag Kontaktierung einer halbleiterzone
US6159852A (en) 1998-02-13 2000-12-12 Micron Technology, Inc. Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor
US6797558B2 (en) * 2001-04-24 2004-09-28 Micron Technology, Inc. Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer
US6319782B1 (en) * 1998-09-10 2001-11-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same
JP2001024194A (ja) * 1999-05-06 2001-01-26 Toshiba Corp 半導体装置の製造方法及び半導体装置
KR20010061029A (ko) * 1999-12-28 2001-07-07 박종섭 엘리베이티드 소오스/드레인 구조의 모스 트랜지스터형성방법
KR100414947B1 (ko) * 2001-06-29 2004-01-16 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 형성 방법
KR100455724B1 (ko) * 2001-10-08 2004-11-12 주식회사 하이닉스반도체 반도체소자의 플러그 형성방법
KR100446316B1 (ko) * 2002-03-30 2004-09-01 주식회사 하이닉스반도체 반도체장치의 콘택플러그 형성 방법
KR100449948B1 (ko) * 2002-05-18 2004-09-30 주식회사 하이닉스반도체 콘택저항을 감소시킨 콘택플러그 형성방법
US7115949B2 (en) * 2002-05-30 2006-10-03 Freescale Semiconductor, Inc. Method of forming a semiconductor device in a semiconductor layer and structure thereof
KR100517328B1 (ko) * 2002-09-17 2005-09-28 주식회사 하이닉스반도체 선택적 에피택셜 성장법을 이용한 콘택플러그를 갖는반도체소자 및 그의 제조 방법
KR100485690B1 (ko) 2002-10-26 2005-04-27 삼성전자주식회사 모스 트랜지스터 및 그 제조방법
KR100505456B1 (ko) * 2002-11-27 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 랜딩 플러그 형성방법
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7247528B2 (en) * 2004-02-24 2007-07-24 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques
JP2005290358A (ja) * 2004-03-08 2005-10-20 Ichikawa Co Ltd 製紙機械用ベルト及びその製造方法
KR100616495B1 (ko) 2004-07-29 2006-08-25 주식회사 하이닉스반도체 실리콘 박막과 실리콘막 사이의 격자 부정합을 줄일 수있는 반도체 소자 제조 방법
KR100605585B1 (ko) 2005-06-20 2006-07-31 주식회사 하이닉스반도체 이중층 고상에피택시실리콘을 패드플러그로서 갖는 반도체소자 및 제조방법
US7989297B2 (en) * 2009-11-09 2011-08-02 International Business Machines Corporation Asymmetric epitaxy and application thereof
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US10032672B1 (en) 2017-08-02 2018-07-24 United Microelectronics Corp. Method of fabricating a semiconductor device having contact structures
CN114695266A (zh) * 2020-12-30 2022-07-01 长鑫存储技术有限公司 存储节点接触结构的形成方法及半导体结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL163372C (nl) * 1967-11-14 1980-08-15 Sony Corp Halfgeleiderinrichting, omvattende een monokristallijn halfgeleiderlichaam met een door aangroeien vanuit de dampfase verkregen halfgeleidende laag, die een gebied van monokristallijn materiaal en een gebied van polykristallijn materiaal omvat.
JPS59186367A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4528047A (en) * 1984-06-25 1985-07-09 International Business Machines Corporation Method for forming a void free isolation structure utilizing etch and refill techniques
IT1213192B (it) * 1984-07-19 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'.
US4592792A (en) * 1985-01-23 1986-06-03 Rca Corporation Method for forming uniformly thick selective epitaxial silicon
US4841347A (en) * 1985-10-30 1989-06-20 General Electric Company MOS VLSI device having shallow junctions and method of making same
JPS6344725A (ja) * 1986-04-02 1988-02-25 Toshiba Corp 半導体装置の製造方法
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US4786615A (en) * 1987-08-31 1988-11-22 Motorola Inc. Method for improved surface planarity in selective epitaxial silicon
US5010034A (en) * 1989-03-07 1991-04-23 National Semiconductor Corporation CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron
US4963506A (en) * 1989-04-24 1990-10-16 Motorola Inc. Selective deposition of amorphous and polycrystalline silicon
KR920008886B1 (ko) * 1989-05-10 1992-10-10 삼성전자 주식회사 디램셀 및 그 제조방법

Also Published As

Publication number Publication date
DE69031753D1 (de) 1998-01-08
JPH0384961A (ja) 1991-04-10
DE69031753T2 (de) 1998-04-23
US5124276A (en) 1992-06-23
KR940000827B1 (ko) 1994-02-02
EP0415537A3 (en) 1991-10-09
EP0415537A2 (en) 1991-03-06
EP0415537B1 (en) 1997-11-26
JPH0671073B2 (ja) 1994-09-07
US5057899A (en) 1991-10-15

Similar Documents

Publication Publication Date Title
KR910005383A (ko) 반도체장치 및 그 제조방법
EP0371862A3 (en) Method of forming a nonsilicon semiconductor on insulator structure
EP0251767A3 (en) Insulated gate type semiconductor device and method of producing the same
KR880014691A (ko) 반도체 장치의 제조방법
KR920017250A (ko) 반도체기판 및 그 제조방법
KR900005589A (ko) 반도체 집적회로 장치 및 그 제조방법
KR920008848A (ko) 표면적이 극대화된 도전층 제조방법
WO2003049191A3 (de) Bicmos-struktur, verfahren zu ihrer herstellung und bipolartransistor für eine bicmos-struktur
KR850004178A (ko) 유전체 분리형 집적회로 장치의 제조방법
KR950012686A (ko) 반도체장치 및 그 제조방법
ATE544176T1 (de) Selektives basisätzen
KR900017091A (ko) 반도체장치 및 그 제조방법
SE9504150L (sv) Förfarande vid tillverkning av en halvledaranordning
KR920017213A (ko) 반도체 장치의 소자격리 방법
KR910005472A (ko) 반도체 소자의 dc 제조 방법
KR880010508A (ko) 반도체장치와 그 제조방법
KR940016463A (ko) 반도체집적회로장치 및 그 제조방법
KR960035920A (ko) 반도체장치 제조방법
KR920005384A (ko) 반도체 장치 및 그 제조방법
KR960002559A (ko) 반도체소자의 금속 배선 형성방법
KR860000704A (ko) 반도 체장치의 제법
KR920013753A (ko) 실리콘단결정을 이용한 기판 및 그의 제조방법
KR970052785A (ko) 반도체 소자 제조방법
KR960026542A (ko) 트렌치 형성방법
KR930017090A (ko) 배선막구조 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030130

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee