KR920017250A - 반도체기판 및 그 제조방법 - Google Patents

반도체기판 및 그 제조방법 Download PDF

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Publication number
KR920017250A
KR920017250A KR1019920002380A KR920002380A KR920017250A KR 920017250 A KR920017250 A KR 920017250A KR 1019920002380 A KR1019920002380 A KR 1019920002380A KR 920002380 A KR920002380 A KR 920002380A KR 920017250 A KR920017250 A KR 920017250A
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KR
South Korea
Prior art keywords
layer
wafer
semiconductor substrate
protection film
major plane
Prior art date
Application number
KR1019920002380A
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English (en)
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KR960016834B1 (ko
Inventor
다카노부 가마쿠라
요우지 야마시타
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR920017250A publication Critical patent/KR920017250A/ko
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Publication of KR960016834B1 publication Critical patent/KR960016834B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

내용 없음

Description

반도체기판 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 반도체기판의 제조방법을 설명하기 위한 도면, 제2도는 OSF체크의 실험결과를 설명하기 위한 도면.

Claims (4)

  1. 웨이퍼(2)의 제1주평면에는 에피택셜성장층(4)이 형성되어 있고, 제2주평면에는 훼손층(3) 및 이 훼손층(3)을 덮으면서 웨이퍼와는 다른 에칭보호막(5)이 형성되어 있으며, 상기 에피택셜성장층(4)이 상기 에칭보호막(5)을 상기 훼손층(3)상에 형성한 상태에서 성장·형성된 것임을 특징으로 하는 반도체기판.
  2. 제1항에 있어서, 상기 웨이퍼(2)는 Si이고, 상기 에칭보호막(5)은 Si산화물과 Si질화물 및 Si탄화물에 의해 구성되는 군(群)중 하나인 것을 특징으로 하는 반도체기판.
  3. 제1항 또는 제2항에 있어서, 상기 훼손층(3)은 반경이 0.01∼1㎛인 훼손부위가 105개/㎠이상의 밀도로 형성된 것을 특징으로 하는 반도체기판.
  4. 웨이퍼(2)의 제2주평면상에 훼손층(3)을 형성하는 공정과, 상기 훼손통(3)상에 에칭보호막(5)을 형성하는 공정 및 상기 웨이퍼(2)의 제1주평면상에 에피택셜층(4)을 형성하는 공정을 구비한 것을 특징으로 하는 반도체기판의 제조방법.
    ※참고사항:최초출원 내용에 의하여 공개하는 것임.
KR1019920002380A 1991-02-21 1992-02-18 반도체기판의 제조방법 KR960016834B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3027551A JP2763204B2 (ja) 1991-02-21 1991-02-21 半導体基板及びその製造方法
JP91-027551 1991-02-21

Publications (2)

Publication Number Publication Date
KR920017250A true KR920017250A (ko) 1992-09-26
KR960016834B1 KR960016834B1 (ko) 1996-12-21

Family

ID=12224204

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920002380A KR960016834B1 (ko) 1991-02-21 1992-02-18 반도체기판의 제조방법

Country Status (4)

Country Link
US (1) US5389551A (ko)
EP (1) EP0500130A3 (ko)
JP (1) JP2763204B2 (ko)
KR (1) KR960016834B1 (ko)

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US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
JP2967398B2 (ja) * 1995-09-18 1999-10-25 信越半導体株式会社 シリコンウエーハ内部の不純物分析方法
US5801104A (en) * 1995-10-24 1998-09-01 Micron Technology, Inc. Uniform dielectric film deposition on textured surfaces
US6132522A (en) * 1996-07-19 2000-10-17 Cfmt, Inc. Wet processing methods for the manufacture of electronic components using sequential chemical processing
JPH10335402A (ja) * 1997-06-02 1998-12-18 Mitsubishi Electric Corp 半導体ウェーハの評価方法及び半導体装置の製造方法及びその方法により製造された半導体装置
US6146980A (en) * 1997-06-04 2000-11-14 United Microelectronics Corp. Method for manufacturing silicon substrate having gettering capability
US6022793A (en) * 1997-10-21 2000-02-08 Seh America, Inc. Silicon and oxygen ion co-implantation for metallic gettering in epitaxial wafers
JP3589119B2 (ja) * 1999-10-07 2004-11-17 三菱住友シリコン株式会社 エピタキシャルウェーハの製造方法
US6376335B1 (en) 2000-02-17 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
WO2001054178A1 (en) * 2000-01-20 2001-07-26 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
US6482749B1 (en) * 2000-08-10 2002-11-19 Seh America, Inc. Method for etching a wafer edge using a potassium-based chemical oxidizer in the presence of hydrofluoric acid
EP1284188B1 (en) * 2001-08-10 2007-10-17 Canon Kabushiki Kaisha Method for manufacturing liquid discharge head, substrate for liquid discharge head and method for working substrate
JP4878738B2 (ja) * 2004-04-30 2012-02-15 株式会社ディスコ 半導体デバイスの加工方法
KR101130378B1 (ko) 2004-09-09 2012-03-27 엘지전자 주식회사 식기세척기 및 그 제어방법
CN101165225B (zh) * 2007-08-28 2010-06-02 河北普兴电子科技股份有限公司 一种ic片外延的工艺方法
JP2013229356A (ja) * 2012-04-24 2013-11-07 Mitsubishi Electric Corp Ｓｏｉウェハおよびその製造方法、並びにｍｅｍｓデバイス
JP7200537B2 (ja) * 2018-08-21 2023-01-10 富士フイルムビジネスイノベーション株式会社 半導体基板の製造方法

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Also Published As

Publication number Publication date
EP0500130A3 (en) 1993-03-03
US5389551A (en) 1995-02-14
EP0500130A2 (en) 1992-08-26
JP2763204B2 (ja) 1998-06-11
KR960016834B1 (ko) 1996-12-21
JPH04267339A (ja) 1992-09-22

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