KR900010924A - 반도체 층 성장으로 부터 결함을 제거하기 위한 버퍼구조를 갖는 반도체 장치 - Google Patents

반도체 층 성장으로 부터 결함을 제거하기 위한 버퍼구조를 갖는 반도체 장치 Download PDF

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KR900010924A
KR900010924A KR1019890019297A KR890019297A KR900010924A KR 900010924 A KR900010924 A KR 900010924A KR 1019890019297 A KR1019890019297 A KR 1019890019297A KR 890019297 A KR890019297 A KR 890019297A KR 900010924 A KR900010924 A KR 900010924A
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semiconductor device
group iii
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도시가즈 이노우에
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야마모또 다꾸마
후지쓰 가부시끼가이샤
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Abstract

내용 없음

Description

반도체 층 성장으로부터 결함을 제거하기 위한 버퍼구조를 갖는 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 실시예에 따른 버퍼구조를 도시한 도, 제3도는 제2도의 버퍼구조의 구성 단면도, 제4도는 두번째 실시예에 따른 버퍼구조의 구성 단면도, 제5도는 본 발명에서 제2도의 버퍼구조를 성장시키기 위해 사용된 장치의 도식적인 구성을 도시한 도.

Claims (11)

  1. Ⅲ-V족 화합물 반도체 물질의 첫번째 물질층(13), 첫번째 물질층 위에 제공된 Ⅲ-V족 화합물 반도체 물질의 두번째 물질층(14)로 이루어진 결함의 확대를 지지하기 위한 버퍼구조 위에 형성된 Ⅲ-V족 화합물 반도체 층(15)를 가지며, 상기 두번째 물질층이 변화한 구성단면과 첫번째 Ⅲ족원소와 다른 첫번째 Ⅲ족원소와 두번째 Ⅲ족원소를 포함하고, 두번째 Ⅲ족원소의 함량이 두번째 물질층의 상하 경계로 감소되는 특징을 갖는 반도체 장치.
  2. 청구범위 제1항에 있어서, 두번째 Ⅲ족원소의 함량이 두번째 물질층(14)의 단계적으로 변하는 특징을 갖는 반도체 장치.
  3. 청구범위 제1항에 있어서, 두번째 Ⅲ족원소의 함량이 두번째 물질층(14)에서 연속적으로 변하는 특징을 갖는 반도체 장치.
  4. 청구범위 제1항에 있어서, 두번째 Ⅲ족원소의 함량이 상하 경계에서 0인 것을 특징으로 하는 반도체 장치.
  5. 청구범위 제1항에 있어서, 거기에 두번째 물질층(14)에서 두번째 Ⅲ족원소의 함량으로 최대인 것을 특징으로 하는 반도체 장치.
  6. 청구범위 제1항에 있어서, 거기에 두번째 물질층(14)에서 두번째 Ⅲ족원소의 함량으로 최대량을 갖는 것을 특징으로 하는 반도체 장치.
  7. 청구범위 제1항에 있어서, 상기 첫번째 Ⅲ족 원소가 갈리움으로 이루어지고, 상기 두번째 Ⅲ족 원소가 인듐으로 이루어진 것을 특징으로 하는 반도체 장치.
  8. 청구범위 제1항에 있어서, 상기 첫번째 물질층(13)이 Ⅲ-V족 화합물 반도체 층(15)의 그것으로부터의 혼합물과 다른 반도체 기판(11) 위에 제공된 것을 특징으로 하는 반도체 장치.
  9. 청구범위 제8항에 있어서, 반도체 기판(11)이 실리콘으로 이루어진 것을 특징으로 하는 반도체 장치.
  10. 청구범위 제1항에 있어서, 첫번째 물질층(13)이 Ⅲ-V족 화합물 반도체 층(15)에서의 혼합물과 같은 Ⅲ-V족 화합물 반도체 기판의 기판을 형성하는 것을 특징으로 하는 반도체 장치.
  11. 청구범위 제10항에 있어서, 첫번째 물질층(13)이 갈리움 아세나이드로 이루어진 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890019297A 1988-12-22 1989-12-22 반도체 층 성장으로 부터 결함을 제거하기 위한 버퍼구조를 갖는 반도체장치. KR930009805B1 (ko)

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Application Number Priority Date Filing Date Title
JP63-325631 1988-12-22
JP88-325631 1988-12-22
JP63325631A JPH02170413A (ja) 1988-12-22 1988-12-22 化合物半導体装置

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KR930009805B1 KR930009805B1 (ko) 1993-10-11

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US (1) US5134446A (ko)
EP (1) EP0375564B1 (ko)
JP (1) JPH02170413A (ko)
KR (1) KR930009805B1 (ko)
DE (1) DE68913479D1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100355636B1 (ko) * 2000-03-10 2002-10-11 광주과학기술원 인듐갈륨알소나이드 콜렉터 에이치비티의 에피택시얼구조

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03136319A (ja) * 1989-10-23 1991-06-11 Fujitsu Ltd ヘテロエピタキシャル基板および半導体装置
CA2062134C (en) * 1991-05-31 1997-03-25 Ibm Heteroepitaxial layers with low defect density and arbitrary network parameter
JP3116731B2 (ja) * 1994-07-25 2000-12-11 株式会社日立製作所 格子不整合系積層結晶構造およびそれを用いた半導体装置
US6423990B1 (en) 1997-09-29 2002-07-23 National Scientific Corporation Vertical heterojunction bipolar transistor
US5912481A (en) * 1997-09-29 1999-06-15 National Scientific Corp. Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction
US6087683A (en) * 1998-07-31 2000-07-11 Lucent Technologies Silicon germanium heterostructure bipolar transistor with indium doped base
US6594293B1 (en) 2001-02-08 2003-07-15 Amberwave Systems Corporation Relaxed InxGa1-xAs layers integrated with Si
US6589335B2 (en) 2001-02-08 2003-07-08 Amberwave Systems Corporation Relaxed InxGa1-xAs layers integrated with Si
WO2002063665A2 (en) * 2001-02-08 2002-08-15 Amberwave Systems Corporation RELAXED InXGa1-xAs LAYERS INTEGRATED WITH Si
US7227174B2 (en) * 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
JP4333426B2 (ja) * 2004-03-19 2009-09-16 ソニー株式会社 化合物半導体の製造方法、及び半導体装置の製造方法
DE102011107657A1 (de) * 2011-07-12 2013-01-17 Nasp Iii/V Gmbh Monolithische integrierte Halbleiterstruktur

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3821033A (en) * 1972-08-03 1974-06-28 Ibm Method for producing flat composite semiconductor substrates
US4568958A (en) * 1984-01-03 1986-02-04 General Electric Company Inversion-mode insulated-gate gallium arsenide field-effect transistors
JPH0650723B2 (ja) * 1984-10-17 1994-06-29 日本電気株式会社 エピタキシヤル成長方法
US4768074A (en) * 1984-11-20 1988-08-30 Kabushiki Kaisha Toshiba Heterojunction bipolar transistor having an emitter region with a band gap greater than that of a base region
US4872046A (en) * 1986-01-24 1989-10-03 University Of Illinois Heterojunction semiconductor device with <001> tilt
US4806996A (en) * 1986-04-10 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories Dislocation-free epitaxial layer on a lattice-mismatched porous or otherwise submicron patterned single crystal substrate
US4769341A (en) * 1986-12-29 1988-09-06 American Telephone And Telegraph Company, At&T Bell Laboratories Method of fabricating non-silicon materials on silicon substrate using an alloy of Sb and Group IV semiconductors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100355636B1 (ko) * 2000-03-10 2002-10-11 광주과학기술원 인듐갈륨알소나이드 콜렉터 에이치비티의 에피택시얼구조

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DE68913479D1 (de) 1994-04-07
US5134446A (en) 1992-07-28
EP0375564A1 (en) 1990-06-27
EP0375564B1 (en) 1994-03-02
KR930009805B1 (ko) 1993-10-11
JPH02170413A (ja) 1990-07-02

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