WO2002063665A2

WO2002063665A2 - RELAXED InXGa1-xAs LAYERS INTEGRATED WITH Si

Info

Publication number: WO2002063665A2
Application number: PCT/US2002/002334
Authority: WO
Inventors: Mayank Bulsara; Eugene A. Fitzgerald
Original assignee: Amberwave Systems Corporation
Priority date: 2001-02-08
Filing date: 2002-01-28
Publication date: 2002-08-15
Also published as: AU2002241984A1; WO2002063665A3

Abstract

A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxially growing a relaxed graded layer of InxGa1-xAs at a temperature ranging upwards from about 600°C with a subsequent process for planarization of the InGaAs alloy.

Description

RELAXED In_xGa!._xAs LAYERS INTEGRATED WITH Si

BACKGROUND OF THE INVENTION

The invention relates to the field of lattice-mismatched epitaxy, and in particular to the field of creating lattice-mismatched devices based on relaxed InGaAs alloys on Si substrates.

Most electronic and optoelectronic devices that require layers deposited by epitaxial growth utilize lattice-matched epitaxial layers, i.e. the crystal structure of the layer has the same lattice constant as that of the substrate. This lattice-matching criterion has been important in creating high quality materials and devices, since lattice-mismatch will create stress and in turn introduce dislocations and other defects into the layers. The dislocations and other defects will often degrade device performance, and more importantly, reduce the reliability of the device.

The applications of lattice-mismatched layers are numerous. In the InGaAs material system, one important composition is in the range of 20-60% In. These compositions allow the fabrication of 1.3 and 1.55 μm optical devices as well as high electron mobility transistors with superior performance on GaAs-based epitaxial layers integrated on Si substrates. Alloys in the desired composition range are lattice- mismatched to GaAs, and thus usually suffer from high dislocation densities. One known method to minimize the number of dislocations reaching the surface of a relaxed, mismatched layer is to compositionally grade the material (in this case through grading the In composition) so that the lattice-mismatch is extended over a great thickness. In addition to the requirement that such layers be low in defect density, the final surface must be smooth with respect to standard optical lithography techniques and the total layer structure InGaAs epitaxial films/GaAs epitaxial films/Si substrate must be able to accommodate thermal expansion mismatch.

Compositional grading is typically accomplished in InGaAs alloys by grading the In composition at a low growth temperature, typically less than 500°C. The dominant technique for depositing relaxed InGaAs layers is molecular beam epitaxy (MBE). MBE has a limited growth rate; therefore, the growth of these relaxed buffers is tedious and costly. In addition, the initial substrate is typically bulk GaAs, not a GaAs epitaxial film of high material quality on Si, and the surface of the InGaAs film is generally not smooth enough for high density optical lithography. A supply of virtual InGaAs substrates (a Si substrate with a high quality, relaxed InGaAs layer at the surface) with a low surface roughness would be in demand commercially. The user could buy the substrate and deposit the device layers without having to deposit the graded InGaAs layer and without introducing the crosshatched surface, which is a signature of compositionally graded films. To create a supply of these wafers at low cost, metalorganic chemical vapor deposition (MOCVD) offers greater potential. In conjunction with MOCVD, a planarization step after the epitaxial process enables InGaAs-on-Si virtual substrates of unprecedented quality.

There have been no successful reports of high quality relaxed graded InGaAs layers grown by MOCVD on GaAs-based epitaxial films on Si substrates. There are fundamental materials problems with InGaAs graded layers grown in a certain temperature window and the provision of a high quality GaAs film on Si has its own inherent challenges.

SUMMARY OF THE INVENTION

It is an object of the invention that with the appropriate grading rate, there is an unforeseen high temperature window, which can be accessed with MOCVD and not MBE, in which high quality relaxed InGaAs alloys can be grown on a GaAs-based epitaxial film on a Si substrate. Relaxed InGaAs grown with MOCVD in this temperature range has the economic advantages of the MOCVD technique, as well as the low defect densities and relaxation associated with high temperature growth. A subsequent planarization step makes the virtual InGaAs-on-Si substrates more suitable for high volume manufacturing.

Another object of the invention is to allow the fabrication of relaxed high quality InGaAs alloys on a Si substrate with the MOCVD technique. These virtual InGaAs substrates can be used in a variety of applications, in particular 1.3 and 1.55 μm optical devices and high-speed microwave transistors. It is a further object of the invention to provide the appropriate conditions during growth in which it is possible to achieve high quality material and devices using this InGaAs/GaAs.

In_xGaι._xAs structures with compositionally graded buffers grown with MOCVD on GaAs substrates and characterized with plan-view and cross-sectional transmission electron microscopy (PV-TEM and X-TEM), atomic force microscopy (AFM), and x-ray diffraction (XRD) show that surface roughness experiences a maximum at growth temperatures near 550°C. The strain fields from misfit dislocations induce a deleterious defect structure in the <110> directions. At growth temperatures above and below this temperature, the surface roughness is decreased significantly; however, only growth temperatures above this regime ensure graded buffer relaxation, uniform composition caps, and high quality material. Using an optimum growth temperature of 700°C for

In_xGaι._xAs grading, it is possible to produce In₀.₃₃Gao.₆₇As diodes on GaAs with threading dislocation densities <8.5 x 10⁶/cm². Although previous experiments have not been carried out on GaAs films on Si substrates, the techniques can be transferred with modifications to address thermal mismatch constraints.

Accordingly, the invention provides a method of processing semiconductor materials, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate; and epitaxially growing a relaxed graded layer of In_xGaι._xAs at a temperature ranging upwards from about 600°C with a subsequent process for planarization of the

InGaAs alloy.

The invention also provides a semiconductor structure including a substrate of a

GaAs epitaxial film on a Si, and a relaxed graded layer of In_xGaι__xAs that is epitaxially grown at a temperature ranging upwards from about 600°C. These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGs. 1 A and IB are schematic process flows of two methods of producing epitaxial GaAs-on-Si virtual substrates;

FIG. 2 is a simplified block diagram of a semiconductor structure in accordance with the invention;

FIG. 3 is a graph illustrating RMS roughness for structures grown at different temperatures; FIG. 4 is a table which shows the growth temperature, composition, and grading rate for nominal xι_n=0.06 structures;

FIG. 5 is a X-TEM micrograph for a xι_n=0.06 In_xGaι._xAs structure grown at 550°C;

FIG. 6 is a X-TEM micrograph for a xι_n=0.06 In_xGaι._xAs structure grown at 700°C;

FIG. 7 is a PV-TEM micrograph of a xι_n=0.06 structure grown at 550°C (g=<220>);

FIG. 8 is an X-TEM micrograph of a xι_n=0.33 In_xGaι__xAs structure grown at 700°C; FIG. 9 is a simplified block diagram of a semiconductor structure of the invention with a device configured thereon; and

FIGs. 10A and 10B are surface scanned images of III-V compound epitaxial graded layers before and after a planarization step.

DETAILED DESCRIPTION OF THE INVENTION

In order to produce a high quality InGaAs epitaxial film on Si, one must first produce a GaAs on Si virtual substrate. FIG. 1A shows an exemplary embodiment of a virtual substrate structure 100. The structure is produced by grading SiGe from 0 to 100%) Ge and depositing a uniform cap of Ge (104) on a Si substrate 102, and thereafter depositing an epitaxial layer 106 of GaAs. Since GaAs is lattice matched to Ge, the grading procedure results in a low defect density, GaAs film. This virtual substrate growth is actually a multi-step process that involves epitaxy, planarization, and careful preparation of the Ge surface prior to the GaAs epitaxy. These processes are described in detail in Currie et. al., Appl. Phys. Lett., 72, 1718 (1998) and Ting et. al., J. Elec. Mater., 27, 451 (1998), both of which are incorporated herein by reference.

FIG. IB is another exemplary embodiment of a GaAs virtual substrate structure 110. This structure is produced by grading SiGe to uniform 100% Ge 114 on a Si substrate 112, and thereafter depositing an epitaxial layer 116 of GaAs, as previously described. After the GaAs/SiGe/Si substrate is produced, it is bonded (118) to a second Si substrate 120 having a semiconductor or dielectric layer 122. The first Si substrate and the SiGe graded layers are subsequently removed (124) to provide a high quality GaAs layer directly on Si, thus the resulting structure 110. Since Ge has a thermal expansion coefficient similar to III-V materials, the removal of the SiGe buffer eliminates a thermally mismatched layer and thus allows for the growth of thicker

InGaAs layers on the GaAs virtual substrate. In addition, the second silicon substrate can have a surface layer dielectric, enabling the production of GaAs/Insulator/Si substrates. The introduction of dielectric layers can be useful as a diffusion barrier between the InGaAs and Si during subsequent device processing. Compositionally graded buffers are implemented in lattice mismatched heteroepitaxy to maintain a low threading dislocation density and to achieve a completely relaxed growth template. MOCVD is a well-established growth technique that is capable of growth rates significantly greater than that of MBE. Therefore, MOCVD is a more practical growth tool for fabricating graded buffers. The ability to grow In_xGai__xAs graded buffers with MOCVD facilitates the manufacture of commercial lattice-mismatched devices, including 1.3μm wavelength emitting lasers on GaAs substrates or virtual GaAs substrates on Si.

In accordance with the invention, In_xGaι._xAs graded buffers are grown on GaAs substrates with MOCVD at different growth temperatures. FIG. 2 is a simplistic block diagram of a semiconductor structure 200 including a substrate 202 of epitaxial GaAs on

Si, on which is grown a relaxed graded layer 204 of In_xGaι._xAs. Exemplary samples were grown in a Thomas Swan atmospheric research reactor on bulk n⁺ GaAs substrates.

The buffers were characterized with plan-view and cross-sectional transmission electron microscopy (PV-TEM and X-TEM), atomic force microscopy (AFM), and x-ray diffraction (XRD). The PV-TEM and X-TEM characterization were done with a JEOL 2000FX microscope. The XRD was performed with a Bede D³ triple axis diffractometer. The AFM experiments were conducted with a Digital Instruments D3000 Nanoscope. In order to explore graded In_xGaι._xAs relaxation, exemplary samples were graded to xi_n∞O.06 (« 0.4%) mismatch). Such a small amount of mismatch produces excellent relaxed layers independent of most growth parameters.

Undoped In_xGaι._xAs graded buffers with nominal final indium concentration of xi_n=0.06 were grown at temperatures between 500-700°C. In addition, x_ln=0.15 and xi_n=0.33 graded buffers were grown at 700°C. All growths were performed with a 5000 sccm H₂ carrier flow and 134 sccm AsH₃ flow. The trimethylgallium (TMG) flow was fixed at 0.030 sccm throughout the graded buffer growth sequence. Compositional grading was accomplished by stepping the trimethylindium (TMI) flow rate by approximately 0.005 sccm up to a final flow rate. This final rate was 0.031 sccm for the xi_n=0.06 graded buffer, 0.077 sccm for the x_ln=0.15 graded buffer, and 0.163 sccm for the graded buffer. Sufficient vent times at the growth temperature were incorporated after each change in TMI flow setting to ensure the growth of the expected composition. All samples, except the structure with the xι_n=0.33 graded buffer, had an undoped lμm uniform cap layer 106. The sample with a xι_n=0.33 graded buffer had a 2μm cap which incorporated a Zn and Si doped PIN diode structure. For the X[_n=0.33, the compositionally graded layer was also doped n-type with Si.

A visual inspection of the surface morphology reveals a strong dependence on growth temperature, a surprising result for such a low lattice mismatch. AFM surface topology data taken on lOμm x lOμm areas of each sample, including the xι_n=0.15 and xι_n=0.33 structures is depicted in the graph of FIG. 3. The data shows that the rms roughness for the nominal X[_n=0.06 sample grown at 550 °C has a significantly greater rms roughness value (52 nm) than the other structures with an rms value of about 10 nm.

In fact, despite the low mismatch, the sample grown at 550°C is not specular to the eye, i.e., it is visibly rough. In addition, the surface roughness for the equivalent x_ln=0.33 structure grown at 700°C was less than the surface roughness of xι_n=0.06 structures grown at lower temperatures.

A criterion for applications is that there must be a great amount of strain relief in conjunction with a low threading dislocation density. To determine the degree of strain relaxation and the indium composition, glancing exit (224) reciprocal space maps were conducted with triple axis XRD. Since the xι_n=0.06 structures were of low mismatch and relatively thin (2μm), the effect of epilayer tilt was expected to be negligible, and thus no glancing incidence (224) or (004) reciprocal space maps were acquired to extract this effect.

X-TEM was used to measure the thickness and, in combination with the final composition, the grading rate. FIG. 4 is a table which shows the growth temperature, composition, and grading rate for the nominal xι_n=0.06 structures. The table shows that the indium composition steadily increased with decreasing temperature (with the exception of the structure grown at 600°C), which is due to the lower cracking temperature for TMI. In addition, the growth rate decreased with decreasing temperature, which in turn provided for a higher grading rate at lower temperature. It should be noted that there is a small error (∞30θA) in the measurement of the graded buffer thickness due to the calibration of the TEM and the tilting of the TEM specimens.

FIG. 4 shows the residual strain in each of the nominal X[_n=0.06 structures as a function of temperature. The structure grown at 500°C had a noticeably greater residual strain in the structure, and there is no general trend among the other samples. However, since the compositions and grading rates differed, the efficiency of the graded buffers at relieving strain was compared by calculating the equilibrium plastic strain rate (strain/thickness) and the overall equilibrium plastic strain. The equilibrium plastic rate is given by

where C is the mismatch introduction rate (misfit/thickness), Y is the Young's modulus, and h is the film height. D is given by D = G6/[2(l-v)] where G is the shear modulus, v is Poisson's ratio, and b is the magnitude of the Bergers vector (60° dislocations are assumed). The expression for the overall plastic deformation in a graded buffer is:

S_eq (h) = C_δ (h)h (2)

The percentage of the equilibrium strain relieved (percent relaxation) is also listed in the table of FIG. 4. All the samples showed a similar degree of relaxation (∞80- 85%o). At such a low mismatch, it is difficult to distinguish the most effective growth conditions for strain relief. The disparities in strain relief were expected to be more pronounced at higher indium compositions. In general, higher growth temperatures allow for more efficient strain relief.

The X-TEM and XRD data exhibit differences in microstructure between the xi_n=0.06 sample grown at 550°C and the same structure grown at 700°C, which is in agreement with the drastic difference in surface morphology. FIGs. 5 and 6 show the X- TEM micrographs of these two structures. Both structures have threading dislocation densities below the X-TEM limit (<10⁸/cm²). Thus, the very poor structure morphology of the 550°C sample is not due to a very high defect density in the top In_xGaι__xAs layer. The uniform cap layer of the structure grown at 550°C does show additional semicircular regions in the top of the film. These features are not dislocations, as the contrast is weak, but rather can be attributed to variations in strain from neighboring regions that may have undergone phase separation during growth. However, recent studies show that high-energy defects are formed in this temperature range, and they may be responsible for the strain contrast although their origin is uncertain. Regardless, growth temperatures in this range near 550°C lead to rough surface morphology which later leads to high threading dislocation densities. A (224) glancing exit reciprocal space map of this structure shows a significantly greater spread in the 2Θ direction for the uniform cap than any of the other samples grown at different temperatures. The FWHM data for the XRD peaks from the uniform caps are listed in the table of FIG. 4. It will be appreciated that the sharpest peak in the 2Θ direction is from the sample grown at 700°C. The spread in the 2Θ direction for the 550°C sample is consistent with a spread in lattice constant due to indium composition variations or defect formations. In addition, the spread in the ω direction (FWHM data also tabulated in the table of FIG. 4) for the cap in the structure grown at 550°C was less than that of the other xι_n=0.06 samples, creating a circular projection of the (224) spot in reciprocal space, as opposed to the typical elliptical spot expected from a high quality relaxed heterostructure.

FIG. 7 shows a plan view TEM image of the xm=0.06 In_xGaι._xAs structure grown at 550°C showing striations under a g=<220> diffraction condition in <110> directions (the same direction as the dislocations in the graded buffer), which may be attributed to compositional variations due to phase separation and/or defect formation at the boundaries between regions. These striations disappear under the other g=<220> condition and g=<400> conditions.

The data suggests that there is a correlation between the dislocations in the graded buffer and the observed boundary defects, which in turn causes the drastic surface roughening in the temperature regime where phase separation is favored. In the low temperature growth regime (500°C), the surface roughening is kinetically limited, as the atoms do not have the mobility to attach to sites that cause the long-range variations seen at higher growth temperatures. In the high temperature growth regime (>600°C), thermodynamics dictate the growth conditions, as the growth occurs above the point at which such boundary defects are favorable.

At the growth temperatures within the range 500-600°C, strained regions with boundaries form, as shown in FIG. 7. These features occur along the <110> direction since the misfit dislocations, strain fields, and cross-hatch surface lie along the <110> directions. As a consequence, the In_xGaι__xAs layers roughen as surface energy is created and as strain energy is relieved. It will be appreciated that this roughening, i.e., very pronounced cross-hatch pattern, is much more severe than the roughening that occurs in systems that lack this apparent phase instability.

Although the X-TEM image of the x_In=0.06 structure grown at 550°C did not show threading dislocations, it has been shown in the Si_xGeι._x materials system that a rough surface with increasing lattice mismatch will eventually lead to a high threading dislocation density. This phenomenon even occurs in structures with slow grading rates and is described in detail in Samavedam et al., "Novel Dislocation Structure and Surface Morphology Effects in Relaxed Ge/SiGe/Si Structures", J. Appl. Phys., 81(7), 3108 (1997), incorporated herein by reference. Grading to greater indium compositions at

550°C produces very rough surfaces that eventually lead to high threading dislocation densities. Although surface roughness can be decreased by growing at lower temperature, this low surface roughness cannot be achieved without compromising the relaxation of the graded buffer. This dependency implies that the only window for growth of In_xGaι._xAs graded buffers that are relaxed and have good surface morphology is at high temperature. It is important to note that MBE can not attain such high growth temperatures due to limited arsenic overpressure.

With surface roughness and relaxation conditions determined to be optimum at a growth temperature of 700°C, a xι_n=0.33 device structure was grown. FIG. 8 is an X- TEM micrograph of this structure. No threading dislocations could be observed in PV- TEM, showing that the threading dislocation density in this structure is <8.5 x 10⁶/cm² given this size of viewable area in TEM. Glancing incidence (224) and glancing exit Θ/2Θ double axis XRD scans show the composition to be xι_n=0.33 and the structure to be 99.39% relaxed.

Accordingly, it has been demonstrated that growth of In_xGaι__xAs graded buffers is sensitive to the growth temperature. In the temperature range approximately between 500 and 600°C, the surface morphology of the structures degrades and rapidly leads to poor quality layers, even at relatively low mismatch. Only growth at higher temperatures produces relaxed layers with sufficient relaxation, good surface morphology, and low threading dislocation densities. The low threading dislocation densities are sufficient for the fabrication of electronic and optoelectronic devices such as 1.3μm wavelength emitting lasers.

FIG. 9 is a simplified block diagram of a semiconductor structure 900 of the invention with a device configured thereon. As shown in FIG. 9, once a virtual substrate 902 of In_xGaι._xAs is created, new optoelectronic and electronic devices can be configured on top of the structure. For example, analogous to heterostructures grown on GaAs substrate, heterostructure devices composed of other alloy compositions can now be fabricated on these substrates. Initially, an InGaAs graded layer 904 and uniform cap layer 906 can be provided on the substrate 902. Layers 908, 910, 912 provided thereafter can be layers of the Al_y(In_xGaι__x)ι._yAs alloy family. These alloys can be used to create 1.3μm heterostructure layers on epitaxial GaAs-on-Si substrates, a great advantage over the 1.3μm devices that need to be grown on InP substrates due to the lattice- matching criterion. In the illustrated embodiment, layers 908 and 912 are the cladding layers of a heterostructure laser, and layer 910 is the active region.

Similar heterostructures from the Al_y(In_xGaι._x)ι._yAs alloy system on these In_xGaι. _xAs buffer layers can be fabricated into high transconductance field effect transistors (FETs) useful in microwave applications. The virtual substrate (InGaAs-on-Si substrate) allows the electron channel or active region (layer 910 in FIG. 9) to be composed of much higher In concentrations than FETs grown on GaAs without the virtual buffer. The higher In concentration in the channel results in very high electron mobilities, and the large band off-sets that can be created in the Al_y(In_xGaι._x)ι._yAs heterostructure system

(910-912) create a very high electron concentration in the channel. Thus, the high mobility and high electron concentrations lead to transistors with very high transconductance.

Although InGaAs alloys of low defect density can be fabricated via epitaxial alloys alone, even greater quality buffers can be created through combination with other improvements for graded layers, such as the use of planarization techniques to lower defect densities in graded buffers or the finishing of the surface after epitaxy to allow for a superior surface for optical lithography. FIGs. 10A and 10B show AFM images of InGaP graded layers on GaP substrate after epitaxy and after epitaxy and a planarization step, respectively. The rms roughness after the planarization step is far improved from the original surface after epitaxy. Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.

What is claimed is:

Claims

CLAIMS L A semiconductor structure, comprising: a Si substrate; a GaAs epitaxial film on said Si substrate, said epitaxial film having a threading dislocation density of less than 10⁷ cm^"2; and a graded layer of In_xGaι._xAs epitaxially grown on said epitaxial film ranging upwards from about 600°C with a final uniform composition layer of In_yGaι__yAs. 2. The structure of claim 1, wherein said In_yGaι._yAs epitaxial layer is planarized.

3. The structure of claim 1, wherein said uniform composition layer of In_yGaι. _yAs includes an indium fraction of at least 20%. 4. The structure of claim 1, wherein said uniform composition layer of In_yGaι. _yAs is at least 500nm. 5. The structure of claim 1, wherein said uniform composition layer of In_yGau

7 7 _yAs has a threading dislocation density less than 10 cm^' . 6. The structure of claim 1, wherein said GaAs epitaxial film on Si is at least 90% relaxed. 7. The structure of claim 1, wherein said graded layer is graded in indium content at a gradient of less than 15%> indium per micrometer. 8. The structure of claim 1, wherein said graded layer and said uniform composition layer are grown via organometallic vapor phase epitaxy. 9. The structure of claim 1 further comprising an epitaxially grown compositionally graded layer of Ge_zSiι_₂ between said GaAs epitaxial film and said Si substrate. 10. The structure of claim 1 further comprising an epitaxially grown compositionally graded layer with at least one planarization step during processing between said GaAs epitaxial film and said Si substrate. 11. The structure of claim 1 further comprising providing an insulator between said GaAs epitaxial film and said Si substrate. 12. The structure of claim 1 further comprising a diffusion barrier between said GaAs epitaxial film and said Si substrate. 13. The structure of claim 2 further comprising a III-V compound laser structure epitaxially grown on said planarized In_yGaι__yAs epitaxial film.

14. The structure of claim 13, wherein said structure comprises an integrated circuit. 15. The structure of claim 2, wherein a III-V compound laser structure is wafer bonded to said planarized In_yGaι._yAs epitaxial film. 16. The structure of claim 15, wherein said structure comprises an integrated circuit. 17. The structure of claim 2 further comprising a III-V compound field effect transistor structure epitaxially grown on said planarized In_yGaι__yAs epitaxial film. 18. The structure of claim 17, wherein said structure comprises an integrated circuit. 19. The structure of claim 2, wherein a III-V compound field effect transistor structure is wafer bonded to said planarized In_yGaι._yAs epitaxial film. 20. The structure of claim 19, wherein said structure comprises an integrated circuit. 21. An integrated circuit comprising: a semiconductor structure, comprising: a Si substrate; a GaAs epitaxial film on said Si substrate, said epitaxial film having a threading

7 7 dislocation density of less than 10 cm^" ; and a graded layer of In_xGaι._xAs epitaxially grown on said epitaxial film ranging upwards from about 600°C with a final uniform composition layer of In_yGaι._yAs. 22. The circuit of claim 21, wherein said In_yGaι__yAs epitaxial layer is planarized.

23. The circuit of claim 21, wherein said uniform composition layer of In_yGaι. _yAs includes an indium fraction of at least 20%>. 24. The circuit of claim 21, wherein said uniform composition layer of In_yGaι_ _yAs is at least 500nm. 25. The circuit of claim 21, wherein said uniform composition layer of In_yGaι. _yAs has a threading dislocation density less than 10⁷ cm^"2. 26. The circuit of claim 21, wherein said GaAs epitaxial film on Si is at least 90%o relaxed. 27. The circuit of claim 21, wherein said graded layer is graded in indium content at a gradient of less than 15%) indium per micrometer. 28. The circuit of claim 21, wherein said graded layer and said uniform composition layer are grown via organometallic vapor phase epitaxy. 29. The circuit of claim 21 further comprising an epitaxially grown compositionally graded layer of Ge_zSiι._z between said GaAs epitaxial film and said Si substrate. 30. The circuit of claim 21 further comprising an epitaxially grown compositionally graded layer with at least one planarization step during processing between said GaAs epitaxial film and said Si substrate. 31. The circuit of claim 21 further comprising providing an insulator between said GaAs epitaxial film and said Si substrate. 32. The circuit of claim 21 further comprising a diffusion barrier between said GaAs epitaxial film and said Si substrate. 33. The circuit of claim 22 further comprising a III-V compound laser structure epitaxially grown on said planarized In_yGaι._yAs epitaxial film. 34. The circuit of claim 22, wherein a III-V compound laser structure is wafer bonded to said planarized In_yGaι__yAs epitaxial film. 35. The circuit of claim 22 further comprising a III-V compound field effect transistor structure epitaxially grown on said planarized In_yGaι._yAs epitaxial film. 36. The circuit of claim 22, wherein a III-V compound field effect transistor structure is wafer bonded to said planarized In_yGaι__yAs epitaxial film. 37. A method of processing semiconductor materials, comprising: providing a GaAs epitaxial film on a Si substrate, said epitaxial film having a threading dislocation density of less than 10⁷ cm^"2; and epitaxially growing a graded layer of In_xGaι._xAs ranging upwards from about 600°C with a final uniform composition layer of In_yGaι__yAs. 38. The method of claim 37 further comprising planarizing said In_yGaι._yAs epitaxial layer. 39. The method of claim 37, wherein said uniform composition layer of In_yGaι._yAs includes an indium fraction of at least 20%. 40. The method of claim 37, wherein said uniform composition layer of In_yGaι_ _yAs is at least 500nm. 41. The method of claim 37, wherein said uniform composition layer of In_yGaι.

7 7 _yAs has a threading dislocation density less than 10 cm^" . 42. The method of claim 37, wherein said GaAs epitaxial film on Si is at least 90% relaxed.

43. The method of claim 37, wherein said graded layer is graded in indium content at a gradient of less than 15% indium per micrometer. 44. The method of claim 37, wherein said graded layer and said uniform composition layer are grown via organometallic vapor phase epitaxy. 45. The method of claim 37 further comprising providing an epitaxially grown compositionally graded layer of Ge_zSiι._z between said GaAs epitaxial film and said Si substrate. 46. The method of claim 37 further comprising providing an epitaxially grown compositionally graded layer with at least one planarization step during processing between said GaAs epitaxial film and said Si substrate. 47. The method of claim 37 further comprising providing an insulator between said GaAs epitaxial film and said Si substrate. 48. The method of claim 37 further comprising providing a diffusion barrier between said GaAs epitaxial film and said Si substrate. 49. The method of claim 38 further comprising epitaxially growing a III-V compound laser structure on said planarized In_yGaι__yAs epitaxial film. 50. The method of claim 38, wherein a III-V compound laser structure is wafer bonded to said planarized In_yGaι„_yAs epitaxial film. 51. The method of claim 38 further comprising epitaxially growing a III-V compound field effect transistor structure on said planarized In_yGaι._yAs epitaxial film. 52. The method of claim 38, wherein a III-V compound field effect transistor structure is wafer bonded to said planarized In_yGaι-_yAs epitaxial film.