KR100376237B1 - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR100376237B1
KR100376237B1 KR10-2000-0061878A KR20000061878A KR100376237B1 KR 100376237 B1 KR100376237 B1 KR 100376237B1 KR 20000061878 A KR20000061878 A KR 20000061878A KR 100376237 B1 KR100376237 B1 KR 100376237B1
Authority
KR
South Korea
Prior art keywords
film
silicon
semiconductor
trench
sti
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2000-0061878A
Other languages
English (en)
Korean (ko)
Other versions
KR20010051166A (ko
Inventor
구니끼요다쯔야
Original Assignee
미쓰비시덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰비시덴키 가부시키가이샤 filed Critical 미쓰비시덴키 가부시키가이샤
Publication of KR20010051166A publication Critical patent/KR20010051166A/ko
Application granted granted Critical
Publication of KR100376237B1 publication Critical patent/KR100376237B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/17Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR10-2000-0061878A 1999-11-11 2000-10-20 반도체 장치 및 그 제조 방법 Expired - Fee Related KR100376237B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32132999A JP2001144170A (ja) 1999-11-11 1999-11-11 半導体装置およびその製造方法
JP1999-321329 1999-11-11

Publications (2)

Publication Number Publication Date
KR20010051166A KR20010051166A (ko) 2001-06-25
KR100376237B1 true KR100376237B1 (ko) 2003-03-15

Family

ID=18131386

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-0061878A Expired - Fee Related KR100376237B1 (ko) 1999-11-11 2000-10-20 반도체 장치 및 그 제조 방법

Country Status (5)

Country Link
US (2) US6333232B1 (https=)
JP (1) JP2001144170A (https=)
KR (1) KR100376237B1 (https=)
DE (1) DE10051600C2 (https=)
TW (1) TW497203B (https=)

Families Citing this family (138)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555449B1 (en) 1996-05-28 2003-04-29 Trustees Of Columbia University In The City Of New York Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidfication
US20020064928A1 (en) * 1999-12-22 2002-05-30 Houston Theodore W. Method for manufacturing a high-frequency integrated circuit for reducing cross-talk and facilitating energy storage
US6830993B1 (en) * 2000-03-21 2004-12-14 The Trustees Of Columbia University In The City Of New York Surface planarization of thin silicon films during and after processing by the sequential lateral solidification method
JP3629187B2 (ja) * 2000-06-28 2005-03-16 株式会社東芝 電気フューズ、この電気フューズを備えた半導体装置及びその製造方法
KR100390143B1 (ko) * 2000-08-17 2003-07-04 삼성전자주식회사 소이층 밴딩 방지 방법 및 그 방법에 의해 형성되는반도체 장치
KR100854834B1 (ko) 2000-10-10 2008-08-27 더 트러스티스 오브 컬럼비아 유니버시티 인 더 시티 오브 뉴욕 얇은 금속층을 가공하는 방법 및 장치
CN1200320C (zh) * 2000-11-27 2005-05-04 纽约市哥伦比亚大学托管会 用激光结晶化法加工衬底上半导体薄膜区域的方法和掩模投影系统
US6582827B1 (en) * 2000-11-27 2003-06-24 The Trustees Of Columbia University In The City Of New York Specialized substrates for use in sequential lateral solidification processing
KR20020042251A (ko) * 2000-11-30 2002-06-05 박종섭 반도체 소자의 분리구조 제조방법
US6882571B1 (en) 2000-12-19 2005-04-19 Xilinx, Inc. Low voltage non-volatile memory cell
US6496416B1 (en) * 2000-12-19 2002-12-17 Xilinx, Inc. Low voltage non-volatile memory cell
JP2002203894A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 半導体装置の製造方法
US7060573B2 (en) * 2001-01-16 2006-06-13 Chartered Semiconductor Manufacturing Ltd. Extended poly buffer STI scheme
US6583488B1 (en) * 2001-03-26 2003-06-24 Advanced Micro Devices, Inc. Low density, tensile stress reducing material for STI trench fill
US6498383B2 (en) * 2001-05-23 2002-12-24 International Business Machines Corporation Oxynitride shallow trench isolation and method of formation
KR20020096137A (ko) * 2001-06-18 2002-12-31 주식회사 하이닉스반도체 반도체 소자의 격리막 제조방법
JP2003017595A (ja) * 2001-06-29 2003-01-17 Toshiba Corp 半導体装置
KR100408862B1 (ko) * 2001-06-29 2003-12-06 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
US6599813B2 (en) * 2001-06-29 2003-07-29 International Business Machines Corporation Method of forming shallow trench isolation for thin silicon-on-insulator substrates
KR100421046B1 (ko) * 2001-07-13 2004-03-04 삼성전자주식회사 반도체 장치 및 그 제조방법
KR100387531B1 (ko) * 2001-07-30 2003-06-18 삼성전자주식회사 반도체소자 제조방법
US6667224B1 (en) 2001-08-13 2003-12-23 Cypress Semiconductor Corp. Method to eliminate inverse narrow width effect in small geometry MOS transistors
US7160763B2 (en) * 2001-08-27 2007-01-09 The Trustees Of Columbia University In The City Of New York Polycrystalline TFT uniformity through microstructure mis-alignment
KR100428768B1 (ko) * 2001-08-29 2004-04-30 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성 방법
KR100421911B1 (ko) * 2001-09-20 2004-03-11 주식회사 하이닉스반도체 반도체 소자의 격리 영역 형성 방법
JP2003100869A (ja) * 2001-09-27 2003-04-04 Toshiba Corp 半導体装置とその製造方法
JP3577024B2 (ja) * 2001-10-09 2004-10-13 エルピーダメモリ株式会社 半導体装置及びその製造方法
US7560385B2 (en) * 2001-10-17 2009-07-14 Texas Instruments Incorporated Etching systems and processing gas specie modulation
JP2003163262A (ja) * 2001-11-28 2003-06-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4139105B2 (ja) * 2001-12-20 2008-08-27 株式会社ルネサステクノロジ 半導体装置の製造方法
US6677211B2 (en) * 2002-01-14 2004-01-13 Macronix International Co., Ltd. Method for eliminating polysilicon residue
US6780730B2 (en) * 2002-01-31 2004-08-24 Infineon Technologies Ag Reduction of negative bias temperature instability in narrow width PMOS using F2 implantation
KR100442615B1 (ko) * 2002-03-05 2004-08-02 삼성전자주식회사 정전용량 감소를 위한 적층구조 및 그 제조방법
WO2003084688A2 (en) * 2002-04-01 2003-10-16 The Trustees Of Columbia University In The City Of New York Method and system for providing a thin film
JP2003309192A (ja) * 2002-04-17 2003-10-31 Fujitsu Ltd 不揮発性半導体メモリおよびその製造方法
TWI291719B (en) * 2002-05-14 2007-12-21 Nanya Technology Corp Method for forming floating gate
US6759302B1 (en) * 2002-07-30 2004-07-06 Taiwan Semiconductor Manufacturing Company Method of generating multiple oxides by plasma nitridation on oxide
US6777281B1 (en) * 2002-08-08 2004-08-17 Advanced Micro Devices, Inc. Maintaining LDD series resistance of MOS transistors by retarding dopant segregation
AU2003265498A1 (en) * 2002-08-19 2004-03-03 The Trustees Of Columbia University In The City Of New York Process and system for laser crystallization processing of film regions on a substrate to provide substantial uniformity within areas in such regions and edge areas thereof, and a structure of such film regions
AU2003272222A1 (en) 2002-08-19 2004-03-03 The Trustees Of Columbia University In The City Of New York Process and system for laser crystallization processing of film regions on a substrate to minimize edge areas, and structure of such film regions
WO2004017379A2 (en) * 2002-08-19 2004-02-26 The Trustees Of Columbia University In The City Of New York Process and system for processing a thin film sample and thin film structure
TWI331803B (en) 2002-08-19 2010-10-11 Univ Columbia A single-shot semiconductor processing system and method having various irradiation patterns
US6884638B1 (en) * 2002-08-20 2005-04-26 Advanced Micro Devices, Inc. Method of fabricating a flash memory semiconductor device by determining the active region width between shallow trench isolation structures using an overdrive current measurement technique and a device thereby fabricated
US6784075B2 (en) * 2002-09-10 2004-08-31 Silicon Integrated Systems Corp. Method of forming shallow trench isolation with silicon oxynitride barrier film
US6930920B1 (en) 2002-10-29 2005-08-16 Xilinx, Inc. Low voltage non-volatile memory cell
KR100480897B1 (ko) * 2002-12-09 2005-04-07 매그나칩 반도체 유한회사 반도체소자의 소자분리막 형성방법
KR100829367B1 (ko) * 2002-12-17 2008-05-13 동부일렉트로닉스 주식회사 반도체 소자의 트렌치 제조 방법
KR101191837B1 (ko) 2003-02-19 2012-10-18 더 트러스티스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 순차적 측면 고상화 기술을 이용하여 결정화되는 복수의 반도체 박막을 가공하는 방법 및 장치
TW200421560A (en) * 2003-04-10 2004-10-16 Macronix Int Co Ltd Method for improvement of edge breakdown caused by edge electrical field at a tunnel oxide of a high-density flash memory by a shielded bird's beak
KR100554836B1 (ko) * 2003-06-30 2006-03-03 주식회사 하이닉스반도체 플래시 메모리 소자의 제조방법
US7342289B2 (en) * 2003-08-08 2008-03-11 Taiwan Semiconductor Manufacturing Co., Ltd Strained silicon MOS devices
US6974755B2 (en) * 2003-08-15 2005-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure with nitrogen-containing liner and methods of manufacture
WO2005029546A2 (en) 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York Method and system for providing a continuous motion sequential lateral solidification for reducing or eliminating artifacts, and a mask for facilitating such artifact reduction/elimination
US7318866B2 (en) 2003-09-16 2008-01-15 The Trustees Of Columbia University In The City Of New York Systems and methods for inducing crystallization of thin films using multiple optical paths
WO2005029547A2 (en) 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York Enhancing the width of polycrystalline grains with mask
WO2005029551A2 (en) 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York Processes and systems for laser crystallization processing of film regions on a substrate utilizing a line-type beam, and structures of such film regions
WO2005029550A2 (en) * 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York Method and system for producing crystalline thin films with a uniform crystalline orientation
TWI351713B (en) 2003-09-16 2011-11-01 Univ Columbia Method and system for providing a single-scan, con
WO2005029548A2 (en) * 2003-09-16 2005-03-31 The Trustees Of Columbia University In The City Of New York System and process for providing multiple beam sequential lateral solidification
US7164152B2 (en) 2003-09-16 2007-01-16 The Trustees Of Columbia University In The City Of New York Laser-irradiated thin films having variable thickness
US7364952B2 (en) 2003-09-16 2008-04-29 The Trustees Of Columbia University In The City Of New York Systems and methods for processing thin films
US7311778B2 (en) 2003-09-19 2007-12-25 The Trustees Of Columbia University In The City Of New York Single scan irradiation for crystallization of thin films
KR100571405B1 (ko) * 2003-12-24 2006-04-14 동부아남반도체 주식회사 반도체 소자의 소자 분리막 형성 방법
US7112513B2 (en) * 2004-02-19 2006-09-26 Micron Technology, Inc. Sub-micron space liner and densification process
JP4577680B2 (ja) * 2004-04-13 2010-11-10 エルピーダメモリ株式会社 半導体装置の製造方法
JP2005340327A (ja) 2004-05-25 2005-12-08 Renesas Technology Corp 半導体装置及びその製造方法
US7176104B1 (en) * 2004-06-08 2007-02-13 Integrated Device Technology, Inc. Method for forming shallow trench isolation structure with deep oxide region
US20060038293A1 (en) * 2004-08-23 2006-02-23 Rueger Neal R Inter-metal dielectric fill
US7271464B2 (en) * 2004-08-24 2007-09-18 Micron Technology, Inc. Liner for shallow trench isolation
US7645337B2 (en) 2004-11-18 2010-01-12 The Trustees Of Columbia University In The City Of New York Systems and methods for creating crystallographic-orientation controlled poly-silicon films
US7271463B2 (en) * 2004-12-10 2007-09-18 Micron Technology, Inc. Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base
JP4961668B2 (ja) * 2005-01-11 2012-06-27 富士電機株式会社 半導体装置の製造方法
US8221544B2 (en) 2005-04-06 2012-07-17 The Trustees Of Columbia University In The City Of New York Line scan sequential lateral solidification of thin films
JP2006310625A (ja) * 2005-04-28 2006-11-09 Toshiba Corp 半導体記憶装置
KR100670666B1 (ko) * 2005-06-28 2007-01-17 주식회사 하이닉스반도체 반도체 소자 제조 방법
US20070018278A1 (en) * 2005-07-25 2007-01-25 Michael Kund Semiconductor memory device
US7432148B2 (en) * 2005-08-31 2008-10-07 Micron Technology, Inc. Shallow trench isolation by atomic-level silicon reconstruction
US7183162B1 (en) * 2005-11-21 2007-02-27 Intel Corporation Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method
WO2007067541A2 (en) 2005-12-05 2007-06-14 The Trustees Of Columbia University In The City Of New York Systems and methods for processing a film, and thin films
KR100734670B1 (ko) * 2005-12-26 2007-07-02 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
US7767515B2 (en) * 2006-02-27 2010-08-03 Synopsys, Inc. Managing integrated circuit stress using stress adjustment trenches
JP5524443B2 (ja) * 2006-03-24 2014-06-18 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US7491622B2 (en) 2006-04-24 2009-02-17 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer formed using an inductively coupled plasma
US7528078B2 (en) 2006-05-12 2009-05-05 Freescale Semiconductor, Inc. Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
KR100865853B1 (ko) * 2006-06-29 2008-10-29 주식회사 하이닉스반도체 소자 분리막을 포함하는 반도체 소자 및 그것의 형성 방법
US7790540B2 (en) * 2006-08-25 2010-09-07 International Business Machines Corporation Structure and method to use low k stress liner to reduce parasitic capacitance
JP4836730B2 (ja) 2006-09-26 2011-12-14 株式会社東芝 半導体装置、およびその製造方法
JP2008124211A (ja) * 2006-11-10 2008-05-29 Fujitsu Ltd 半導体装置の製造方法
US7879663B2 (en) * 2007-03-08 2011-02-01 Freescale Semiconductor, Inc. Trench formation in a semiconductor material
US7691693B2 (en) * 2007-06-01 2010-04-06 Synopsys, Inc. Method for suppressing layout sensitivity of threshold voltage in a transistor array
JP2008300779A (ja) * 2007-06-04 2008-12-11 Elpida Memory Inc 半導体装置及びその製造方法
US7781306B2 (en) * 2007-06-20 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same
US20090039458A1 (en) * 2007-08-10 2009-02-12 Qimonda Ag Integrated device
US8614471B2 (en) 2007-09-21 2013-12-24 The Trustees Of Columbia University In The City Of New York Collections of laterally crystallized semiconductor islands for use in thin film transistors
JP5385289B2 (ja) 2007-09-25 2014-01-08 ザ トラスティーズ オブ コロンビア ユニヴァーシティ イン ザ シティ オブ ニューヨーク 横方向に結晶化した薄膜上に作製される薄膜トランジスタデバイスにおいて高い均一性を生成する方法
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
US20090108408A1 (en) * 2007-10-29 2009-04-30 Synopsys, Inc. Method for Trapping Implant Damage in a Semiconductor Substrate
US9472423B2 (en) * 2007-10-30 2016-10-18 Synopsys, Inc. Method for suppressing lattice defects in a semiconductor substrate
US8012861B2 (en) 2007-11-21 2011-09-06 The Trustees Of Columbia University In The City Of New York Systems and methods for preparing epitaxially textured polycrystalline films
WO2009067688A1 (en) 2007-11-21 2009-05-28 The Trustees Of Columbia University In The City Of New York Systems and methods for preparing epitaxially textured polycrystalline films
KR20100105606A (ko) 2007-11-21 2010-09-29 더 트러스티이스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 에피택셜하게 텍스쳐화된 후막의 제조를 위한 시스템 및 방법
US7902611B1 (en) 2007-11-27 2011-03-08 Altera Corporation Integrated circuit well isolation structures
US8569155B2 (en) 2008-02-29 2013-10-29 The Trustees Of Columbia University In The City Of New York Flash lamp annealing crystallization for large area thin films
US8125037B2 (en) 2008-08-12 2012-02-28 International Business Machines Corporation Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage
US7838353B2 (en) * 2008-08-12 2010-11-23 International Business Machines Corporation Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method
US8237233B2 (en) * 2008-08-19 2012-08-07 International Business Machines Corporation Field effect transistor having a gate structure with a first section above a center portion of the channel region and having a first effective work function and second sections above edges of the channel region and having a second effective work function
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
KR101506901B1 (ko) * 2008-10-15 2015-03-30 삼성전자주식회사 반도체 소자의 제조 방법
KR20110094022A (ko) 2008-11-14 2011-08-19 더 트러스티이스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 박막 결정화를 위한 시스템 및 방법
KR100987794B1 (ko) * 2008-12-22 2010-10-13 한국전자통신연구원 반도체 장치의 제조 방법
JP2010153583A (ja) * 2008-12-25 2010-07-08 Renesas Electronics Corp 半導体装置の製造方法
JP5629450B2 (ja) * 2009-10-16 2014-11-19 キヤノン株式会社 半導体素子及び半導体素子の形成方法
US8440581B2 (en) 2009-11-24 2013-05-14 The Trustees Of Columbia University In The City Of New York Systems and methods for non-periodic pulse sequential lateral solidification
US9087696B2 (en) 2009-11-03 2015-07-21 The Trustees Of Columbia University In The City Of New York Systems and methods for non-periodic pulse partial melt film processing
US9646831B2 (en) 2009-11-03 2017-05-09 The Trustees Of Columbia University In The City Of New York Advanced excimer laser annealing for thin films
US8987818B1 (en) 2009-11-13 2015-03-24 Maxim Integrated Products, Inc. Integrated MOS power transistor with thin gate oxide and low gate charge
US8946851B1 (en) 2009-11-13 2015-02-03 Maxim Integrated Products, Inc. Integrated MOS power transistor with thin gate oxide and low gate charge
US20110115019A1 (en) * 2009-11-13 2011-05-19 Maxim Integrated Products, Inc. Cmos compatible low gate charge lateral mosfet
US8963241B1 (en) 2009-11-13 2015-02-24 Maxim Integrated Products, Inc. Integrated MOS power transistor with poly field plate extension for depletion assist
US8969958B1 (en) 2009-11-13 2015-03-03 Maxim Integrated Products, Inc. Integrated MOS power transistor with body extension region for poly field plate depletion assist
US20110115018A1 (en) * 2009-11-13 2011-05-19 Maxim Integrated Products, Inc. Mos power transistor
US10672748B1 (en) 2010-06-02 2020-06-02 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional heterogeneous technologies integration
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies
US9484269B2 (en) * 2010-06-24 2016-11-01 Globalfoundries Inc. Structure and method to control bottom corner threshold in an SOI device
KR20120133652A (ko) * 2011-05-31 2012-12-11 삼성전자주식회사 반도체 소자의 제조 방법
EP2573807A1 (en) * 2011-09-23 2013-03-27 Soitec Semiconductor structure and process for bird's beak reduction
US8679929B2 (en) * 2011-12-06 2014-03-25 Texas Instruments Incorporated On current in one-time-programmable memory cells
US20150087135A1 (en) * 2013-09-26 2015-03-26 Texas Instruments Incorporated Method of forming a trench isolation structure using a sion layer
JP6334370B2 (ja) 2014-11-13 2018-05-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10707330B2 (en) 2018-02-15 2020-07-07 Globalfoundries Inc. Semiconductor device with interconnect to source/drain
JP2018133585A (ja) * 2018-04-26 2018-08-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10636870B2 (en) * 2018-08-15 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation regions for reduced junction leakage
CN110970345B (zh) * 2018-09-29 2024-12-06 长鑫存储技术有限公司 半导体结构及制备方法
CN113517193B (zh) * 2021-04-06 2022-03-11 江苏新顺微电子股份有限公司 一种提高沟槽mos结构肖特基二极管性能的工艺方法
CN115915749B (zh) * 2023-01-19 2023-06-02 合肥晶合集成电路股份有限公司 半导体结构及其制作方法
CN119922935B (zh) * 2025-01-17 2026-02-17 长飞先进半导体(武汉)有限公司 半导体器件及制作方法、功率模块、功率转换电路和车辆
CN120656992B (zh) * 2025-08-20 2025-12-16 合肥晶合集成电路股份有限公司 一种浅沟槽隔离结构的制造方法及浅沟槽隔离结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980074323A (ko) * 1997-03-24 1998-11-05 문정환 반도체 소자의 셜로우 트렌치 아이솔레이션 방법

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447884A (en) 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
JPH08203884A (ja) * 1995-01-31 1996-08-09 Mitsubishi Electric Corp オキシナイトライド膜およびその形成方法ならびにそのオキシナイトライド膜を用いた素子分離酸化膜の形成方法
JPH08213382A (ja) * 1995-02-02 1996-08-20 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH0982794A (ja) * 1995-09-20 1997-03-28 Matsushita Electric Ind Co Ltd トレンチ分離形成方法
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
JP3604791B2 (ja) 1995-11-09 2004-12-22 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3688816B2 (ja) * 1996-07-16 2005-08-31 株式会社東芝 半導体装置の製造方法
US5780346A (en) * 1996-12-31 1998-07-14 Intel Corporation N2 O nitrided-oxide trench sidewalls and method of making isolation structure
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
JPH10303289A (ja) * 1997-04-30 1998-11-13 Hitachi Ltd 半導体集積回路装置の製造方法
JPH113936A (ja) 1997-06-13 1999-01-06 Nec Corp 半導体装置の製造方法
JP3125719B2 (ja) 1997-07-28 2001-01-22 日本電気株式会社 半導体装置及びその製造方法
JPH1167752A (ja) * 1997-08-08 1999-03-09 Mitsubishi Electric Corp 半導体装置の製造方法
US6143625A (en) * 1997-11-19 2000-11-07 Texas Instruments Incorporated Protective liner for isolation trench side walls and method
US6008109A (en) * 1997-12-19 1999-12-28 Advanced Micro Devices, Inc. Trench isolation structure having a low K dielectric encapsulated by oxide
JP3519589B2 (ja) * 1997-12-24 2004-04-19 株式会社ルネサステクノロジ 半導体集積回路の製造方法
TW407335B (en) * 1998-01-23 2000-10-01 United Microelectronics Corp Method of producing shallow trench isolation
US6074932A (en) * 1998-01-28 2000-06-13 Texas Instruments - Acer Incorporated Method for forming a stress-free shallow trench isolation
TW368727B (en) * 1998-03-17 1999-09-01 United Microelectronics Corp Manufacturing method for shallow trench isolation structure
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
US6156620A (en) * 1998-07-22 2000-12-05 Lsi Logic Corporation Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
KR100292616B1 (ko) * 1998-10-09 2001-07-12 윤종용 트렌치격리의제조방법
KR100315441B1 (ko) * 1999-03-25 2001-11-28 황인길 반도체 소자 분리를 위한 얕은 트렌치 제조 방법
JP2001085511A (ja) * 1999-09-14 2001-03-30 Toshiba Corp 素子分離方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980074323A (ko) * 1997-03-24 1998-11-05 문정환 반도체 소자의 셜로우 트렌치 아이솔레이션 방법

Also Published As

Publication number Publication date
DE10051600A1 (de) 2001-05-23
US20020022326A1 (en) 2002-02-21
JP2001144170A (ja) 2001-05-25
US6333232B1 (en) 2001-12-25
KR20010051166A (ko) 2001-06-25
TW497203B (en) 2002-08-01
DE10051600C2 (de) 2003-05-08
US6495424B2 (en) 2002-12-17

Similar Documents

Publication Publication Date Title
KR100376237B1 (ko) 반도체 장치 및 그 제조 방법
US7402473B2 (en) Semiconductor device and process for producing the same
US6285061B1 (en) Structure and method for fabricating a field effect transistor with a self-aligned anti-punchthrough implant channel
US7227230B2 (en) Low-K gate spacers by fluorine implantation
US6004852A (en) Manufacture of MOSFET having LDD source/drain region
US5994179A (en) Method of fabricating a MOSFET featuring an effective suppression of reverse short-channel effect
US7682927B2 (en) Method of manufacturing semiconductor device
KR20000006444A (ko) Mos트랜지스터의제조방법
KR20030003087A (ko) 반도체 집적 회로 장치 및 그 제조 방법
JP3530026B2 (ja) 半導体装置及びその製造方法
GB2392557A (en) Semiconductor device and method of manufacture
KR100458767B1 (ko) 반도체 소자의 소자 분리막 형성 방법
US6639264B1 (en) Method and structure for surface state passivation to improve yield and reliability of integrated circuit structures
US6358818B1 (en) Method for forming trench isolation regions
US6281084B1 (en) Disposable spacers for improved array gapfill in high density DRAMs
US6803315B2 (en) Method for blocking implants from the gate of an electronic device via planarizing films
US20040053458A1 (en) Semiconductor device with element isolation using impurity-doped insulator and oxynitride film
KR100361764B1 (ko) 반도체소자의 소자분리막 형성방법
JP3644682B2 (ja) 半導体装置の製造方法
US7081419B2 (en) Gate dielectric structure for reducing boron penetration and current leakage
KR20040050826A (ko) 반도체 장치 및 반도체 장치의 제조 방법
KR100490303B1 (ko) 반도체 소자의 제조 방법
KR20010068540A (ko) 반도체 메모리 장치의 콘택 패드 형성 방법
KR100414742B1 (ko) 반도체소자의소자분리절연막형성방법
KR100606952B1 (ko) 반도체 소자의 트랜지스터 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20090225

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20100305

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20100305

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000