JP4577680B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4577680B2 JP4577680B2 JP2004117798A JP2004117798A JP4577680B2 JP 4577680 B2 JP4577680 B2 JP 4577680B2 JP 2004117798 A JP2004117798 A JP 2004117798A JP 2004117798 A JP2004117798 A JP 2004117798A JP 4577680 B2 JP4577680 B2 JP 4577680B2
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- Prior art keywords
- oxide film
- semiconductor device
- annealing
- manufacturing
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
Description
2 パッド酸化膜
3 窒化膜
4 トレンチ
5 内壁酸化膜
6 埋設酸化膜
7 犠牲酸化膜
8 ゲート酸化膜
9 ディポッド
Claims (5)
- トレンチを含む分離領域と、当該分離領域によって分離された活性領域を基板上に設けると共に、前記活性領域にゲート電極膜を有する素子を形成する半導体装置の製造方法において、前記トレンチに埋設される埋設酸化膜成長後から前記ゲート電極膜の成長前までのいずれかの工程で、前記基板を絶縁膜で覆った状態で、希ガスからなる雰囲気中で、1000℃以上、1200℃以下の温度で、且つ、10分以上、5時間以下の条件下でアニール処理して、前記分離領域と接し、前記活性領域の境界部を形成する肩部の断面形状を前記アニール処理前に比較して丸くすることを特徴とする半導体装置の製造方法。
- 前記希ガスは、アルゴン、ネオン、ヘリウムであることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記アニール処理は、前記素子のチャンネル領域を形成する前に行われることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記アニール処理は、前記埋設酸化膜成長後、当該埋設酸化膜をCMPによって平坦化する前に行われることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記アニール処理は、前記素子のゲート絶縁膜形成後、前記素子の前記ゲート電極膜形成前に行われることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004117798A JP4577680B2 (ja) | 2004-04-13 | 2004-04-13 | 半導体装置の製造方法 |
US11/103,613 US20050227452A1 (en) | 2004-04-13 | 2005-04-12 | Method for producing semiconductor device |
CN200510064979.XA CN1684242A (zh) | 2004-04-13 | 2005-04-13 | 半导体器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004117798A JP4577680B2 (ja) | 2004-04-13 | 2004-04-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005303044A JP2005303044A (ja) | 2005-10-27 |
JP4577680B2 true JP4577680B2 (ja) | 2010-11-10 |
Family
ID=35061100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004117798A Expired - Fee Related JP4577680B2 (ja) | 2004-04-13 | 2004-04-13 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20050227452A1 (ja) |
JP (1) | JP4577680B2 (ja) |
CN (1) | CN1684242A (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7432148B2 (en) * | 2005-08-31 | 2008-10-07 | Micron Technology, Inc. | Shallow trench isolation by atomic-level silicon reconstruction |
US8125037B2 (en) | 2008-08-12 | 2012-02-28 | International Business Machines Corporation | Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage |
US7838353B2 (en) * | 2008-08-12 | 2010-11-23 | International Business Machines Corporation | Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method |
CN102446762B (zh) * | 2010-10-13 | 2014-02-05 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其制作方法 |
CN102332400B (zh) * | 2011-07-28 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | 半导体器件的形成方法 |
US9945048B2 (en) * | 2012-06-15 | 2018-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012674A (ja) * | 1998-06-19 | 2000-01-14 | Toshiba Corp | 半導体装置の製造方法および素子分離方法 |
JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002057211A (ja) * | 2000-08-15 | 2002-02-22 | Seiko Epson Corp | トレンチ素子分離領域を有する半導体装置の製造方法 |
JP2004006660A (ja) * | 2002-03-26 | 2004-01-08 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2004273971A (ja) * | 2003-03-12 | 2004-09-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69211329T2 (de) * | 1992-03-27 | 1996-11-28 | Ibm | Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur |
JP4420986B2 (ja) * | 1995-11-21 | 2010-02-24 | 株式会社東芝 | シャロウ・トレンチ分離半導体基板及びその製造方法 |
JPH1079421A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
US6322634B1 (en) * | 1997-01-27 | 2001-11-27 | Micron Technology, Inc. | Shallow trench isolation structure without corner exposure |
US6097076A (en) * | 1997-03-25 | 2000-08-01 | Micron Technology, Inc. | Self-aligned isolation trench |
US5849643A (en) * | 1997-05-23 | 1998-12-15 | Advanced Micro Devices, Inc. | Gate oxidation technique for deep sub quarter micron transistors |
US6566224B1 (en) * | 1997-07-31 | 2003-05-20 | Agere Systems, Inc. | Process for device fabrication |
KR100261018B1 (ko) * | 1997-09-25 | 2000-08-01 | 윤종용 | 반도체장치의트렌치격리형성방법 |
US6087243A (en) * | 1997-10-21 | 2000-07-11 | Advanced Micro Devices, Inc. | Method of forming trench isolation with high integrity, ultra thin gate oxide |
TW389982B (en) * | 1998-01-26 | 2000-05-11 | United Microelectronics Corp | Method of manufacturing shallow trench isolation |
KR100275908B1 (ko) * | 1998-03-02 | 2000-12-15 | 윤종용 | 집적 회로에 트렌치 아이솔레이션을 형성하는방법 |
US5989978A (en) * | 1998-07-16 | 1999-11-23 | Chartered Semiconductor Manufacturing, Ltd. | Shallow trench isolation of MOSFETS with reduced corner parasitic currents |
KR100292616B1 (ko) * | 1998-10-09 | 2001-07-12 | 윤종용 | 트렌치격리의제조방법 |
KR100338767B1 (ko) * | 1999-10-12 | 2002-05-30 | 윤종용 | 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법 |
US6277697B1 (en) * | 1999-11-12 | 2001-08-21 | United Microelectronics Corp. | Method to reduce inverse-narrow-width effect |
US6413828B1 (en) * | 2000-03-08 | 2002-07-02 | International Business Machines Corporation | Process using poly-buffered STI |
US6455382B1 (en) * | 2001-05-03 | 2002-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step method for forming sacrificial silicon oxide layer |
JP3597495B2 (ja) * | 2001-08-31 | 2004-12-08 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6713335B2 (en) * | 2002-08-22 | 2004-03-30 | Chartered Semiconductor Manufacturing Ltd. | Method of self-aligning a damascene gate structure to isolation regions |
US7091105B2 (en) * | 2002-10-28 | 2006-08-15 | Hynix Semiconductor Inc. | Method of forming isolation films in semiconductor devices |
CN100437970C (zh) * | 2003-03-07 | 2008-11-26 | 琥珀波系统公司 | 一种结构及用于形成半导体结构的方法 |
KR100505068B1 (ko) * | 2003-07-05 | 2005-07-29 | 삼성전자주식회사 | 반도체 소자의 다중 게이트 산화막 및 이를 포함하는게이트 전극 형성방법 |
US7018873B2 (en) * | 2003-08-13 | 2006-03-28 | International Business Machines Corporation | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate |
JP4550453B2 (ja) * | 2004-03-23 | 2010-09-22 | 株式会社東芝 | 工程管理システム、及び工程管理方法 |
-
2004
- 2004-04-13 JP JP2004117798A patent/JP4577680B2/ja not_active Expired - Fee Related
-
2005
- 2005-04-12 US US11/103,613 patent/US20050227452A1/en not_active Abandoned
- 2005-04-13 CN CN200510064979.XA patent/CN1684242A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012674A (ja) * | 1998-06-19 | 2000-01-14 | Toshiba Corp | 半導体装置の製造方法および素子分離方法 |
JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002057211A (ja) * | 2000-08-15 | 2002-02-22 | Seiko Epson Corp | トレンチ素子分離領域を有する半導体装置の製造方法 |
JP2004006660A (ja) * | 2002-03-26 | 2004-01-08 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2004273971A (ja) * | 2003-03-12 | 2004-09-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2005303044A (ja) | 2005-10-27 |
US20050227452A1 (en) | 2005-10-13 |
CN1684242A (zh) | 2005-10-19 |
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