JPWO2006097982A1 - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法 Download PDFInfo
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Abstract
Description
(a)複数のチップ領域に区画され、前記複数のチップ領域の各々には半導体集積回路が形成され、主面上において前記半導体集積回路と電気的に接続する複数の第1電極が形成された半導体ウエハを用意する工程、
(b)第1配線が形成された第1配線基板と、前記複数の第1電極に接触させるための複数の接触端子および前記複数の接触端子と電気的に接続する第2配線が形成され、前記第2配線が前記第1配線と電気的に接続し前記複数の接触端子の先端が前記半導体ウエハの主面に対向して前記第1配線基板に保持された第1シートと、前記第1シートのうち前記複数の接触端子が形成された第1領域を前記第1配線基板から離間して保持する接着リングと、前記第1シートのうち前記第1領域を裏面側から押し出す押し出し機構と、前記複数の接触端子の前記先端を前記複数の第1電極に接触させる際のコンタクト加圧量を制御する加圧機構とを有する第1カードを用意する工程、
(c)前記複数の接触端子の前記先端を前記複数の第1電極に接触させて前記半導体集積回路の電気的検査を行う工程。
(a)複数のチップ領域に区画され、前記複数のチップ領域の各々には半導体集積回路が形成され、主面上において前記半導体集積回路と電気的に接続する複数の第1電極が形成された半導体ウエハを用意する工程、
(b)第1配線が形成された第1配線基板と、前記複数の第1電極に接触させるための複数の接触端子および前記複数の接触端子と電気的に接続する第2配線が形成され、前記第2配線が前記第1配線と電気的に接続し前記複数の接触端子の先端が前記半導体ウエハの主面に対向して前記第1配線基板に保持された第1シートと、前記第1シートのうち前記複数の接触端子が形成された第1領域を前記第1配線基板から離間して保持する接着リングと、前記第1シートのうち前記第1領域を裏面側から押し出す押し出し機構と、前記複数の接触端子の前記先端を前記複数の第1電極に接触させる際のコンタクト加圧量を制御する加圧機構とを有する第1カードを用意する工程、
(c)前記複数の接触端子の前記先端を前記複数の第1電極に接触させて前記半導体集積回路の電気的検査を行う工程。
前記押し出し機構による前記第1領域の押し出し量と前記加圧機構による前記コンタクト加圧量とは、それぞれ独立に制御される。
1. 第1配線が形成された第1配線基板と、
半導体ウエハの主面に形成された複数の第1電極に接触させるための複数の接触端子および前記複数の接触端子と電気的に接続する第2配線が形成され、前記第2配線が前記第1配線と電気的に接続し前記複数の接触端子の先端が前記半導体ウエハの主面に対向して前記第1配線基板に保持された第1シートと、
前記第1シートのうち前記複数の接触端子が形成された第1領域を前記第1配線基板から離間して保持する接着リングと、
前記第1シートのうち前記第1領域を裏面側から押し出す押し出し機構と、
前記複数の接触端子の前記先端を前記複数の第1電極に接触させる際のコンタクト加圧量を制御する加圧機構とを有し、
前記押し出し機構による前記第1領域の押し出し量と前記加圧機構による前記コンタクト加圧量とは、それぞれ独立に制御されるプローブカード。
2. 第1配線が形成された第1配線基板と、
半導体ウエハの主面に形成された複数の第1電極に接触させるための複数の接触端子および前記複数の接触端子と電気的に接続する第2配線が形成され、前記第2配線が前記第1配線と電気的に接続し前記複数の接触端子の先端が前記半導体ウエハの主面に対向して前記第1配線基板に保持された第1シートと、
前記第1シートのうち前記複数の接触端子が形成された第1領域を前記第1配線基板から離間して保持する接着リングと、
前記第1シートのうち前記第1領域を裏面側から押し出す押し出し機構と、
前記複数の接触端子の前記先端を前記複数の第1電極に接触させる際のコンタクト加圧量を制御する加圧機構とを有し、
前記押し出し機構は、前記第1シートの前記第1領域の前記裏面側に貼付され、
前記押し出し機構による前記第1領域の押し出し量と前記加圧機構による前記コンタクト加圧量とは、それぞれ独立に制御されるプローブカード。
本実施の形態1の半導体集積回路装置は、たとえばLCD(Liquid Crystal Display)ドライバ回路が形成されたチップである。図1および図2は、それぞれそのチップの要部断面図であり、それぞれ異なる断面を示している。
そこで、本実施の形態1においては、図19および図20に示すように、それら配線を2層の配線層(配線23、26)から形成することを例示することができる。なお、配線26およびポリイミド膜25上には、ポリイミド膜27が形成されている。相対的に下層の配線23はポリイミド膜22に形成されたスルーホール24の底部で金属膜21A、21Cと接触し、相対的に上層の配線26はポリイミド膜22、25に形成されたスルーホール28の底部で金属膜21B、21Dと接触している。それにより、同一の配線層においては、隣り合う配線23または配線26の間隔を大きく確保することが可能となるので、隣り合う配線23または配線26が接触してしまう不具合を防ぐことができる。また、パッドPD3が5列以上となり、それに対応するプローブ数が増加して上記距離LXが狭くなる場合には、さらに多層に配線層を形成することによって、配線間隔を広げてもよい。
本実施の形態2は、前記実施の形態1でも説明した薄膜シート2(図7参照)を他の構造としたものである。
図46は本実施の形態3の半導体集積回路装置を形成したチップの要部を示す断面図であり、紙面左側の断面は積層配線が形成された領域を示し、紙面右側の断面はボンディングパッド(以降、単にパッドと記す)が形成された領域を示している。
Claims (12)
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)複数のチップ領域に区画され、前記複数のチップ領域の各々には半導体集積回路が形成され、主面上において前記半導体集積回路と電気的に接続する複数の第1電極が形成された半導体ウエハを用意する工程、
(b)第1配線が形成された第1配線基板と、前記複数の第1電極に接触させるための複数の接触端子および前記複数の接触端子と電気的に接続する第2配線が形成され、前記第2配線が前記第1配線と電気的に接続し前記複数の接触端子の先端が前記半導体ウエハの主面に対向して前記第1配線基板に保持された第1シートと、前記第1シートのうち前記複数の接触端子が形成された第1領域を前記第1配線基板から離間して保持する接着リングと、前記第1シートのうち前記第1領域を裏面側から押し出す押し出し機構と、前記複数の接触端子の前記先端を前記複数の第1電極に接触させる際のコンタクト加圧量を制御する加圧機構とを有する第1カードを用意する工程、
(c)前記複数の接触端子の前記先端を前記複数の第1電極に接触させて前記半導体集積回路の電気的検査を行う工程。
ここで、前記押し出し機構による前記第1領域の押し出し量と前記加圧機構による前記コンタクト加圧量とは、それぞれ独立に制御される。 - 請求項1記載の半導体集積回路装置の製造方法において、
前記接触端子の先端は、前記接着リングより押し出されている。 - 請求項1記載の半導体集積回路装置の製造方法において、
前記(c)工程時において、1つの前記接触端子に加わる荷重は3g未満である。 - 請求項1記載の半導体集積回路装置の製造方法において、
前記半導体ウエハの前記主面上には、SiO2と比べて誘電率の低い絶縁膜が形成されている。 - 請求項1記載の半導体集積回路装置の製造方法において、
前記半導体集積回路は、前記第1電極下に配置されている。 - 請求項1記載の半導体集積回路装置の製造方法において、
前記第1電極は、金を主成分とした突起電極またはアルミニウムを主成分としたパッド電極である。 - 以下の工程を含む半導体集積回路装置の製造方法:
(a)複数のチップ領域に区画され、前記複数のチップ領域の各々には半導体集積回路が形成され、主面上において前記半導体集積回路と電気的に接続する複数の第1電極が形成された半導体ウエハを用意する工程、
(b)第1配線が形成された第1配線基板と、前記複数の第1電極に接触させるための複数の接触端子および前記複数の接触端子と電気的に接続する第2配線が形成され、前記第2配線が前記第1配線と電気的に接続し前記複数の接触端子の先端が前記半導体ウエハの主面に対向して前記第1配線基板に保持された第1シートと、前記第1シートのうち前記複数の接触端子が形成された第1領域を前記第1配線基板から離間して保持する接着リングと、前記第1シートのうち前記第1領域を裏面側から押し出す押し出し機構と、前記複数の接触端子の前記先端を前記複数の第1電極に接触させる際のコンタクト加圧量を制御する加圧機構とを有する第1カードを用意する工程、
(c)前記複数の接触端子の前記先端を前記複数の第1電極に接触させて前記半導体集積回路の電気的検査を行う工程。
ここで、前記押し出し機構は、前記第1シートの前記第1領域の前記裏面側に貼付され、
前記押し出し機構による前記第1領域の押し出し量と前記加圧機構による前記コンタクト加圧量とは、それぞれ独立に制御される。 - 請求項7記載の半導体集積回路装置の製造方法において、
前記接触端子の先端は、前記接着リングより押し出されている。 - 請求項7記載の半導体集積回路装置の製造方法において、
前記(c)工程時において、1つの前記接触端子に加わる荷重は3g未満である。 - 請求項7記載の半導体集積回路装置の製造方法において、
前記半導体ウエハの前記主面上には、SiO2と比べて誘電率の低い絶縁膜が形成されている。 - 請求項8記載の半導体集積回路装置の製造方法において、
前記半導体集積回路は、前記第1電極下に配置されている。 - 請求項9記載の半導体集積回路装置の製造方法において、
前記第1電極は、金を主成分とした突起電極またはアルミニウムを主成分としたパッド電極である。
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JP2004157127A (ja) | 2004-01-05 | 2004-06-03 | Renesas Technology Corp | 半導体装置の製造方法 |
JP4521611B2 (ja) | 2004-04-09 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
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2005
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- 2005-03-11 JP JP2007507953A patent/JP4829879B2/ja not_active Expired - Fee Related
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- 2005-03-11 CN CN200580048884A patent/CN100585826C/zh not_active Expired - Fee Related
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Patent Citations (4)
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JPH0936188A (ja) * | 1995-07-14 | 1997-02-07 | Tokyo Electron Ltd | プローブ装置に用いられるプローブカードデバイス |
JPH10308423A (ja) * | 1997-05-09 | 1998-11-17 | Hitachi Ltd | 半導体素子の製造方法および半導体素子へのプロービング方法 |
JP2001159643A (ja) * | 1999-12-02 | 2001-06-12 | Hitachi Ltd | 接続装置および検査システム |
JP2002134509A (ja) * | 2000-08-31 | 2002-05-10 | Texas Instruments Inc | シリコン・レベル相互接続層の機械的性能を構造的に増強する方法 |
Also Published As
Publication number | Publication date |
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JP4829879B2 (ja) | 2011-12-07 |
CN100585826C (zh) | 2010-01-27 |
TWI371815B (ja) | 2012-09-01 |
US20090017565A1 (en) | 2009-01-15 |
US8357933B2 (en) | 2013-01-22 |
US20100277192A1 (en) | 2010-11-04 |
CN101133487A (zh) | 2008-02-27 |
US7776626B2 (en) | 2010-08-17 |
TW200633103A (en) | 2006-09-16 |
WO2006097982A1 (ja) | 2006-09-21 |
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