JPS5936262U - 半導体メモリ素子 - Google Patents
半導体メモリ素子Info
- Publication number
- JPS5936262U JPS5936262U JP1983097373U JP9737383U JPS5936262U JP S5936262 U JPS5936262 U JP S5936262U JP 1983097373 U JP1983097373 U JP 1983097373U JP 9737383 U JP9737383 U JP 9737383U JP S5936262 U JPS5936262 U JP S5936262U
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- substrate
- semiconductor memory
- semiconductor
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は本考案による半導体メモリ素子の断面図、第2
図は第1図に示したメモリ素子の等価回路図である。 11・・・・・・基板、19.23・・・・・・絶縁層
、17゜21・・・・・・ゲート、31・・・・・・ビ
ット線路。
図は第1図に示したメモリ素子の等価回路図である。 11・・・・・・基板、19.23・・・・・・絶縁層
、17゜21・・・・・・ゲート、31・・・・・・ビ
ット線路。
Claims (2)
- (1)第1導電形の半導体基板と、前記半導体基板上に
形成した絶縁層と、前記絶縁層上に形成したゲートと、
前記絶縁層と前記基板の境界部より前記基板中に前記第
1導電形であるがより高濃度に形成した半導体領域と、
前記基板中に電荷を導入するゲート手段とより成る半導
体メモリ素子。 - (2)前記ゲート手段は、前記半導体基板中に形成した
第2導電形の一対の表面領域と、前記表面領域間で前記
半導体基板上に形成した絶縁層と、前記絶縁層上に形成
したゲートとより成るトランジスタである実用新案登録
請求の範囲第1項記載の半導体メモリ素子。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/838,199 US4163243A (en) | 1977-09-30 | 1977-09-30 | One-transistor memory cell with enhanced capacitance |
US838199 | 2010-07-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5936262U true JPS5936262U (ja) | 1984-03-07 |
Family
ID=25276528
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12032778A Pending JPS5456382A (en) | 1977-09-30 | 1978-09-29 | Semiconductor memory cell |
JP1983097373U Pending JPS5936262U (ja) | 1977-09-30 | 1983-06-23 | 半導体メモリ素子 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12032778A Pending JPS5456382A (en) | 1977-09-30 | 1978-09-29 | Semiconductor memory cell |
Country Status (3)
Country | Link |
---|---|
US (1) | US4163243A (ja) |
JP (2) | JPS5456382A (ja) |
DE (1) | DE2841453C2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61266206A (ja) * | 1985-05-20 | 1986-11-25 | Kobe Steel Ltd | 連続混練機の混練制御装置 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5434438A (en) * | 1976-09-13 | 1995-07-18 | Texas Instruments Inc. | Random access memory cell with a capacitor |
JPS6044752B2 (ja) * | 1978-04-24 | 1985-10-05 | 日本電気株式会社 | ダイナミツクメモリ |
US4320312A (en) * | 1978-10-02 | 1982-03-16 | Hewlett-Packard Company | Smaller memory cells and logic circuits |
US4441246A (en) * | 1980-05-07 | 1984-04-10 | Texas Instruments Incorporated | Method of making memory cell by selective oxidation of polysilicon |
US5109258A (en) * | 1980-05-07 | 1992-04-28 | Texas Instruments Incorporated | Memory cell made by selective oxidation of polysilicon |
JPS5718356A (en) * | 1980-07-07 | 1982-01-30 | Mitsubishi Electric Corp | Semiconductor memory storage |
US4364075A (en) * | 1980-09-02 | 1982-12-14 | Intel Corporation | CMOS Dynamic RAM cell and method of fabrication |
US4373250A (en) * | 1980-11-17 | 1983-02-15 | Signetics Corporation | Process for fabricating a high capacity memory cell |
US4535349A (en) * | 1981-12-31 | 1985-08-13 | International Business Machines Corporation | Non-volatile memory cell using a crystalline storage element with capacitively coupled sensing |
US4887135A (en) * | 1982-02-09 | 1989-12-12 | American Telephone And Telegraph Company, At&T Bell Laboratories | Dual level polysilicon single transistor-capacitor memory array |
US4542481A (en) * | 1983-01-31 | 1985-09-17 | International Business Machines Corporation | One-device random access memory cell having enhanced capacitance |
JPS60126861A (ja) * | 1983-12-13 | 1985-07-06 | Fujitsu Ltd | 半導体記憶装置 |
JPS60128658A (ja) * | 1983-12-15 | 1985-07-09 | Toshiba Corp | 半導体記憶装置 |
JPS6260256A (ja) * | 1985-09-10 | 1987-03-16 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JPS62114265A (ja) * | 1985-11-13 | 1987-05-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2655859B2 (ja) * | 1988-02-03 | 1997-09-24 | 株式会社日立製作所 | 半導体記憶装置 |
US5465249A (en) * | 1991-11-26 | 1995-11-07 | Cree Research, Inc. | Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate |
US5217907A (en) * | 1992-01-28 | 1993-06-08 | National Semiconductor Corporation | Array spreading resistance probe (ASRP) method for profile extraction from semiconductor chips of cellular construction |
US5347226A (en) * | 1992-11-16 | 1994-09-13 | National Semiconductor Corporation | Array spreading resistance probe (ASRP) method for profile extraction from semiconductor chips of cellular construction |
US5714411A (en) * | 1995-01-03 | 1998-02-03 | Motorola, Inc. | Process for forming a semiconductor device including a capacitor |
US6066525A (en) * | 1998-04-07 | 2000-05-23 | Lsi Logic Corporation | Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process |
US7256415B2 (en) * | 2005-05-31 | 2007-08-14 | International Business Machines Corporation | Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells |
FR2893763A1 (fr) * | 2005-11-21 | 2007-05-25 | St Microelectronics Sa | Element de memoire non-volatile |
WO2010114406A1 (ru) * | 2009-03-30 | 2010-10-07 | Murashev Viktor Nikolaevich | Ячейка памяти для быстродействующего эсппзу и способ ее программирования |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS525224A (en) * | 1975-07-02 | 1977-01-14 | Hitachi Ltd | 1trs-type memory cell |
JPS52107786A (en) * | 1976-03-08 | 1977-09-09 | Nec Corp | Integrating circuit |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3740731A (en) * | 1971-08-02 | 1973-06-19 | Texas Instruments Inc | One transistor dynamic memory cell |
US3740732A (en) * | 1971-08-12 | 1973-06-19 | Texas Instruments Inc | Dynamic data storage cell |
US4075045A (en) * | 1976-02-09 | 1978-02-21 | International Business Machines Corporation | Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps |
-
1977
- 1977-09-30 US US05/838,199 patent/US4163243A/en not_active Expired - Lifetime
-
1978
- 1978-09-23 DE DE2841453A patent/DE2841453C2/de not_active Expired
- 1978-09-29 JP JP12032778A patent/JPS5456382A/ja active Pending
-
1983
- 1983-06-23 JP JP1983097373U patent/JPS5936262U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS525224A (en) * | 1975-07-02 | 1977-01-14 | Hitachi Ltd | 1trs-type memory cell |
JPS52107786A (en) * | 1976-03-08 | 1977-09-09 | Nec Corp | Integrating circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61266206A (ja) * | 1985-05-20 | 1986-11-25 | Kobe Steel Ltd | 連続混練機の混練制御装置 |
Also Published As
Publication number | Publication date |
---|---|
DE2841453A1 (de) | 1979-04-12 |
US4163243A (en) | 1979-07-31 |
DE2841453C2 (de) | 1982-07-22 |
JPS5456382A (en) | 1979-05-07 |
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