JPS59112944U - 集積回路 - Google Patents

集積回路

Info

Publication number
JPS59112944U
JPS59112944U JP1983183901U JP18390183U JPS59112944U JP S59112944 U JPS59112944 U JP S59112944U JP 1983183901 U JP1983183901 U JP 1983183901U JP 18390183 U JP18390183 U JP 18390183U JP S59112944 U JPS59112944 U JP S59112944U
Authority
JP
Japan
Prior art keywords
conductivity type
region
integrated circuit
substrate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983183901U
Other languages
English (en)
Inventor
ハロルド・ウオ−レス・ド−チエル
Original Assignee
モステツク・コ−ポレイシヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by モステツク・コ−ポレイシヨン filed Critical モステツク・コ−ポレイシヨン
Publication of JPS59112944U publication Critical patent/JPS59112944U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Waveguides (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
添付図面の第１図は本考案の集積回路装置の一部分の概
略平面図、第２図から第５図は第１図の構造の種々な断
面を示す図である。 １０・・・・・・集積回路装置、１２・・・半導体基板
、１４・・・・・・フィールド酸化物層、１６・・・・
・・狭い通路、１８・・・・・・熱的酸化物層、２０・
・・・・・多結晶シリコンストリップ、２２・・・・・
・絶縁層、２４・・・・・・金属導体、２６・・・・・
・第１の領域、２８・・・・・・第２の領域、３０・・
・・・・第３の領域、３２．　３４．　３６．　３８・
・・・・・回路手段。

Claims (5)

    【実用新案登録請求の範囲】
  1. （１）第１の導電型の半導体基板と、該基板の上方表面
    に沿って該基板中に第１の信号を伝送するための狭い通
    路を形成するフィールド酸化物と、前記基板の上でその
    基板から絶縁され且つ前記狭い通路と交差して第２の信
    号を伝送するための高い導電性の多結晶シリコンストリ
    ップと、該多結晶シリコンストリップの下で前記狭い通
    路に配設され且つ前記基板への不純物のイオンインプラ
    ンテーションによって形成される第２の導電型の第１の
    領域と、前記多結晶シリコンストリップの一方の側で前
    記狭い通路の一部分に形成される第２の導電型の第２の
    領域と、該第２の領域とは反対の前記多結晶シリコンス
    トリップの側で前記狭い通路の一部分に形成される第２
    の導電型の第３の領域とを備えており、前記第２の導電
    型の第１、第２および第３の領域は前記狭い通路に連続
    信号伝送ラインを形成することを特徴とする集積回路。
  2. （２）前記第２および第３の領域は、前記基板へ第２の
    導電型の不純物を拡散することによって形成される実用
    新案登録請求の範囲第１項に記載の集積回路。
  3. （３）前記第１の領域は前記多結晶シリコンストリップ
    の形成前にイオンインプランテーションによって形成さ
    れ、前記第２および第３の領域は前記多結晶シリコンス
    トリップの形成後イオンインプランテーションによって
    形成される実用新案登録請求の範囲第１項記載の集積回
    路。
  4. （４）前記第１の導電型はＰ型であり、前記第２の導電
    型はＮ型である実用新案登録請求の範囲第１楢に記載の
    集積回路。
  5. （５）前記第１の導電型はＮ型であり前記第２の導　゛
    電型はＰ型である実用新案登録請求の範囲第１項番と記
    載の集積回路。
JP1983183901U 1977-07-18 1983-11-30 集積回路 Pending JPS59112944U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81636577A 1977-07-18 1977-07-18
US816365 1977-07-18

Publications (1)

Publication Number Publication Date
JPS59112944U true JPS59112944U (ja) 1984-07-30

Family

ID=25220405

Family Applications (2)

Application Number Title Priority Date Filing Date
JP8760878A Pending JPS5496384A (en) 1977-07-18 1978-07-18 Method of and structure for crossing information signal for ic
JP1983183901U Pending JPS59112944U (ja) 1977-07-18 1983-11-30 集積回路

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP8760878A Pending JPS5496384A (en) 1977-07-18 1978-07-18 Method of and structure for crossing information signal for ic

Country Status (5)

Country Link
JP (2) JPS5496384A (ja)
DE (1) DE2831523A1 (ja)
FR (1) FR2398386A1 (ja)
GB (1) GB2001472B (ja)
IT (1) IT1097967B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550652A (en) * 1978-09-19 1980-04-12 Agency Of Ind Science & Technol Composite element adjusting method by ion beam
US4381595A (en) * 1979-10-09 1983-05-03 Mitsubishi Denki Kabushiki Kaisha Process for preparing multilayer interconnection

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921282A (en) * 1971-02-16 1975-11-25 Texas Instruments Inc Insulated gate field effect transistor circuits and their method of fabrication
US3751722A (en) * 1971-04-30 1973-08-07 Standard Microsyst Smc Mos integrated circuit with substrate containing selectively formed resistivity regions
JPS5947464B2 (ja) * 1974-09-11 1984-11-19 株式会社日立製作所 半導体装置
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
US4035198A (en) * 1976-06-30 1977-07-12 International Business Machines Corporation Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Also Published As

Publication number Publication date
IT1097967B (it) 1985-08-31
FR2398386A1 (fr) 1979-02-16
GB2001472A (en) 1979-01-31
JPS5496384A (en) 1979-07-30
DE2831523A1 (de) 1979-02-01
IT7825819A0 (it) 1978-07-17
GB2001472B (en) 1982-02-17
FR2398386B1 (ja) 1984-03-23

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