IT1097967B - Procedimnto e struttura per l'incrocio di segnali di informazione in un dispositivo a circuito integrato - Google Patents
Procedimnto e struttura per l'incrocio di segnali di informazione in un dispositivo a circuito integratoInfo
- Publication number
- IT1097967B IT1097967B IT25819/78A IT2581978A IT1097967B IT 1097967 B IT1097967 B IT 1097967B IT 25819/78 A IT25819/78 A IT 25819/78A IT 2581978 A IT2581978 A IT 2581978A IT 1097967 B IT1097967 B IT 1097967B
- Authority
- IT
- Italy
- Prior art keywords
- crossing
- procedure
- integrated circuit
- circuit device
- information signals
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Waveguides (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US81636577A | 1977-07-18 | 1977-07-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IT7825819A0 IT7825819A0 (it) | 1978-07-17 |
| IT1097967B true IT1097967B (it) | 1985-08-31 |
Family
ID=25220405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT25819/78A IT1097967B (it) | 1977-07-18 | 1978-07-17 | Procedimnto e struttura per l'incrocio di segnali di informazione in un dispositivo a circuito integrato |
Country Status (5)
| Country | Link |
|---|---|
| JP (2) | JPS5496384A (ja) |
| DE (1) | DE2831523A1 (ja) |
| FR (1) | FR2398386A1 (ja) |
| GB (1) | GB2001472B (ja) |
| IT (1) | IT1097967B (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5550652A (en) * | 1978-09-19 | 1980-04-12 | Agency Of Ind Science & Technol | Composite element adjusting method by ion beam |
| US4381595A (en) * | 1979-10-09 | 1983-05-03 | Mitsubishi Denki Kabushiki Kaisha | Process for preparing multilayer interconnection |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3921282A (en) * | 1971-02-16 | 1975-11-25 | Texas Instruments Inc | Insulated gate field effect transistor circuits and their method of fabrication |
| US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
| JPS5947464B2 (ja) * | 1974-09-11 | 1984-11-19 | 株式会社日立製作所 | 半導体装置 |
| US4013489A (en) * | 1976-02-10 | 1977-03-22 | Intel Corporation | Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit |
| US4035198A (en) * | 1976-06-30 | 1977-07-12 | International Business Machines Corporation | Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors |
-
1978
- 1978-07-17 FR FR7821183A patent/FR2398386A1/fr active Granted
- 1978-07-17 IT IT25819/78A patent/IT1097967B/it active
- 1978-07-18 JP JP8760878A patent/JPS5496384A/ja active Pending
- 1978-07-18 GB GB7830229A patent/GB2001472B/en not_active Expired
- 1978-07-18 DE DE19782831523 patent/DE2831523A1/de not_active Ceased
-
1983
- 1983-11-30 JP JP1983183901U patent/JPS59112944U/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59112944U (ja) | 1984-07-30 |
| GB2001472B (en) | 1982-02-17 |
| GB2001472A (en) | 1979-01-31 |
| FR2398386A1 (fr) | 1979-02-16 |
| DE2831523A1 (de) | 1979-02-01 |
| FR2398386B1 (ja) | 1984-03-23 |
| IT7825819A0 (it) | 1978-07-17 |
| JPS5496384A (en) | 1979-07-30 |
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