FR2398386A1 - Procede et structure pour faire se croiser des signaux d'information dans un dispositif a circuit integre - Google Patents

Procede et structure pour faire se croiser des signaux d'information dans un dispositif a circuit integre

Info

Publication number
FR2398386A1
FR2398386A1 FR7821183A FR7821183A FR2398386A1 FR 2398386 A1 FR2398386 A1 FR 2398386A1 FR 7821183 A FR7821183 A FR 7821183A FR 7821183 A FR7821183 A FR 7821183A FR 2398386 A1 FR2398386 A1 FR 2398386A1
Authority
FR
France
Prior art keywords
integrated circuit
substrate
ion implantation
implantation region
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7821183A
Other languages
English (en)
Other versions
FR2398386B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of FR2398386A1 publication Critical patent/FR2398386A1/fr
Application granted granted Critical
Publication of FR2398386B1 publication Critical patent/FR2398386B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Waveguides (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

La présente invention concerne un procédé et une structure pour faire se croiser des signaux d'information dans un dispositif à circuit intégré. Sur un substrat 12, une bande de silicium polycristallin triconductrice 20, forme une première ligne porteuse de signal au-dessus d'une couche d'oxyde 18. En-dessous du substrat, est disposée une région d'implantation d'ions 26 de type de conductivité opposé à celui du substrat. La région d'implantation d'ions 26 rejoint des régions diffusées 28 et 30 de part et d'autre de la bande de silicium polycristallin. Les régions diffusées sont du même type de conductivité que la région à implatation d'ions, formant ainsi avec celle-ci une seconde ligne porteuse de signaux transverse à la première et la croisant Application à la diminution de la surface occupée par des lignes porteuses de signaux se croisant sur un substrat de circuit intégré.
FR7821183A 1977-07-18 1978-07-17 Procede et structure pour faire se croiser des signaux d'information dans un dispositif a circuit integre Granted FR2398386A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81636577A 1977-07-18 1977-07-18

Publications (2)

Publication Number Publication Date
FR2398386A1 true FR2398386A1 (fr) 1979-02-16
FR2398386B1 FR2398386B1 (fr) 1984-03-23

Family

ID=25220405

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7821183A Granted FR2398386A1 (fr) 1977-07-18 1978-07-17 Procede et structure pour faire se croiser des signaux d'information dans un dispositif a circuit integre

Country Status (5)

Country Link
JP (2) JPS5496384A (fr)
DE (1) DE2831523A1 (fr)
FR (1) FR2398386A1 (fr)
GB (1) GB2001472B (fr)
IT (1) IT1097967B (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5550652A (en) * 1978-09-19 1980-04-12 Agency Of Ind Science & Technol Composite element adjusting method by ion beam
US4381595A (en) * 1979-10-09 1983-05-03 Mitsubishi Denki Kabushiki Kaisha Process for preparing multilayer interconnection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2125462A1 (fr) * 1971-02-16 1972-09-29 Texas Instruments Inc
FR2134468A1 (fr) * 1971-04-30 1972-12-08 Standard Microsystems
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947464B2 (ja) * 1974-09-11 1984-11-19 株式会社日立製作所 半導体装置
US4035198A (en) * 1976-06-30 1977-07-12 International Business Machines Corporation Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2125462A1 (fr) * 1971-02-16 1972-09-29 Texas Instruments Inc
FR2134468A1 (fr) * 1971-04-30 1972-12-08 Standard Microsystems
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol.17, no.10, mars 1975, New York (US) *

Also Published As

Publication number Publication date
IT1097967B (it) 1985-08-31
IT7825819A0 (it) 1978-07-17
DE2831523A1 (de) 1979-02-01
FR2398386B1 (fr) 1984-03-23
JPS5496384A (en) 1979-07-30
GB2001472A (en) 1979-01-31
JPS59112944U (ja) 1984-07-30
GB2001472B (en) 1982-02-17

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Richards The sedimentology of the lower Trias, Western Alps

Legal Events

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TP Transmission of property
ST Notification of lapse