JPS61253U - 自己整列ゲートｃｍｏｓ装置 - Google Patents

自己整列ゲートｃｍｏｓ装置

Info

Publication number
JPS61253U
JPS61253U JP1985074930U JP7493085U JPS61253U JP S61253 U JPS61253 U JP S61253U JP 1985074930 U JP1985074930 U JP 1985074930U JP 7493085 U JP7493085 U JP 7493085U JP S61253 U JPS61253 U JP S61253U
Authority
JP
Japan
Prior art keywords
oxide layer
region
masking
conductivity type
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985074930U
Other languages
English (en)
Inventor
グレゴリオ・スパデア
Original Assignee
ナシヨナル・セミコンダクター・コーポレーシヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ナシヨナル・セミコンダクター・コーポレーシヨン filed Critical ナシヨナル・セミコンダクター・コーポレーシヨン
Publication of JPS61253U publication Critical patent/JPS61253U/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図〜第６図は本考案の自己整列ゲートＣＭＯＳを製
作工程順に示す断面図、第７図〜第１１図は本考案の別
の自己整列ゲー｝ＣＭＯＳを製作工程順に示す断面図、
第１２図〜第１５図は、第１図〜第６図の装置を修正し
た形態の自己整列ゲ−トｃＭＯｓを製作工程順に示す断
面図、第１６図〜第１９図は本考案のさらに別の自己整
列ゲートＣＭＯＳを製作工程順に示す断面図である。 １２二酸化ケイ素、１３：Ｎ基板、１４：Ｐ一領域、１
５：酸化物ゲート層、１６：窒化ケイ素、１７．１７’
：Ｐ＋ソースドレイン領域、１８：Ｐ＋ガードリング、
１９：酸化ケイ素、２１．２１’：Ｎ＋ソースドレイン
領域、２２：Ｎ＋ガードリング、２３二酸化ケイ素、２
４：接触孔、２５：金属接点、３１：ケイ素Ｎ層、３２
：絶縁基板、３４：窒化ケイ素、３５：Ｐ十領域、３６
：酸化ケイ素、３７：フォトレジスト、３８：孔、３９
：Ｐ一領域、４２：Ｎ＋ソースドレイン領域、４３：酸
化ケイ素、４４：金属接点、４５：ゲート電極、５１：
フォトレジスト。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１の電導型の半導体基板の表面上に第１の酸化物層を
    形成し、この第１の酸化物層をマスキングした後、エッ
    チングして第１の酸化物層中の陪基板の第１領域に達す
    る孔を形成し、この第１領域にドニプ剤を拡散させて該
    基板中に第２の電導型の領域を形成し、第１の酸化物層
    の残りを除去し、基板の表面上に第２の酸化物層を形成
    し、この第２の酸化物層の上に窒化ケイ素層を形成し、
    この窒化ケイ素と第２の化物層をマスキングおよびエッ
    チングして、これに前記第１領域と離して孔を形成し、
    この孔を通してドープ剤を拡散させて基板内に前記の第
    ２の電導型のソースおよびドレイン領域を形成し、窒化
    ケイ素と第２の酸化物層をマスキングおよびエッチング
    して前記第１領域上に孔を形成し、この孔を通してドー
    プ剤を拡散させて前記第１領域に前記第１の電導型のソ
    ースおよびドレイン領域を形成し、酸化ケイ素層の各ソ
    ースおよびドレイン領域の上に当る部分をマスキングお
    よびエッチングして前記領域への接触孔を形成し、ゲー
    ト領域の窒化ケイ素層をエッチングで除去し、装置上に
    金属化層を沈着させ、この金属層中に金続接続および接
    続孔を区画するためにマスキングし、金属をエッチング
    してゲート電極とソースおよびドレイン接続子を形成し
    て成ることを特徴とする自己整列ゲー｝ＣＭＯＳ装置。
JP1985074930U 1975-05-08 1985-05-20 自己整列ゲートｃｍｏｓ装置 Pending JPS61253U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/575,655 US3983620A (en) 1975-05-08 1975-05-08 Self-aligned CMOS process for bulk silicon and insulating substrate device
US575655 1984-01-31

Publications (1)

Publication Number Publication Date
JPS61253U true JPS61253U (ja) 1986-01-06

Family

ID=24301188

Family Applications (2)

Application Number Title Priority Date Filing Date
JP51052760A Pending JPS51138174A (en) 1975-05-08 1976-05-08 Method of producing selffarrangement cmos to bulk silicon and insulating substrate device
JP1985074930U Pending JPS61253U (ja) 1975-05-08 1985-05-20 自己整列ゲートｃｍｏｓ装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP51052760A Pending JPS51138174A (en) 1975-05-08 1976-05-08 Method of producing selffarrangement cmos to bulk silicon and insulating substrate device

Country Status (6)

Country Link
US (1) US3983620A (ja)
JP (2) JPS51138174A (ja)
CA (1) CA1057862A (ja)
DE (4) DE2661097C2 (ja)
FR (1) FR2310635A1 (ja)
GB (4) GB1529296A (ja)

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Also Published As

Publication number Publication date
GB1529023A (en) 1978-10-18
DE2661099C2 (ja) 1988-10-20
GB1529298A (en) 1978-10-18
DE2620155A1 (de) 1976-11-18
GB1529297A (en) 1978-10-18
JPS51138174A (en) 1976-11-29
GB1529296A (en) 1978-10-18
DE2620155C2 (ja) 1988-05-19
DE2661097C2 (ja) 1988-05-26
DE2661098C2 (ja) 1989-07-06
US3983620A (en) 1976-10-05
CA1057862A (en) 1979-07-03
FR2310635A1 (fr) 1976-12-03
FR2310635B1 (ja) 1980-02-15

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