IT1210872B - Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate. - Google Patents

Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.

Info

Publication number
IT1210872B
IT1210872B IT8220661A IT2066182A IT1210872B IT 1210872 B IT1210872 B IT 1210872B IT 8220661 A IT8220661 A IT 8220661A IT 2066182 A IT2066182 A IT 2066182A IT 1210872 B IT1210872 B IT 1210872B
Authority
IT
Italy
Prior art keywords
manufacture
integrated circuits
mos transistors
complementary mos
density integrated
Prior art date
Application number
IT8220661A
Other languages
English (en)
Other versions
IT8220661A0 (it
Inventor
Gianfranco Cerofolini
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8220661A priority Critical patent/IT1210872B/it
Publication of IT8220661A0 publication Critical patent/IT8220661A0/it
Priority to US06/482,156 priority patent/US4468852A/en
Priority to JP58059402A priority patent/JPS58202562A/ja
Priority to NLAANVRAGE8301229,A priority patent/NL188607C/xx
Priority to FR8305752A priority patent/FR2525030B1/fr
Priority to GB08309572A priority patent/GB2120844B/en
Priority to DE19833312720 priority patent/DE3312720A1/de
Application granted granted Critical
Publication of IT1210872B publication Critical patent/IT1210872B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
IT8220661A 1982-04-08 1982-04-08 Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate. IT1210872B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8220661A IT1210872B (it) 1982-04-08 1982-04-08 Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.
US06/482,156 US4468852A (en) 1982-04-08 1983-04-05 Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation
JP58059402A JPS58202562A (ja) 1982-04-08 1983-04-06 半導体装置の製造方法
NLAANVRAGE8301229,A NL188607C (nl) 1982-04-08 1983-04-07 Werkwijze voor het vormen van een stel complementaire mos transistoren.
FR8305752A FR2525030B1 (fr) 1982-04-08 1983-04-08 Procede pour la fabrication de transistors mos complementaires dans des circuits integres a haute densite pour tensions elevees
GB08309572A GB2120844B (en) 1982-04-08 1983-04-08 Improvements in or relating to methods of forming cmos transistor pairs
DE19833312720 DE3312720A1 (de) 1982-04-08 1983-04-08 Verfahren zur herstellung von komplementaeren mos-transistoren in hochintegrierten schaltungen fuer hohe spannungen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8220661A IT1210872B (it) 1982-04-08 1982-04-08 Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.

Publications (2)

Publication Number Publication Date
IT8220661A0 IT8220661A0 (it) 1982-04-08
IT1210872B true IT1210872B (it) 1989-09-29

Family

ID=11170208

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8220661A IT1210872B (it) 1982-04-08 1982-04-08 Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.

Country Status (7)

Country Link
US (1) US4468852A (it)
JP (1) JPS58202562A (it)
DE (1) DE3312720A1 (it)
FR (1) FR2525030B1 (it)
GB (1) GB2120844B (it)
IT (1) IT1210872B (it)
NL (1) NL188607C (it)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
JPS60123055A (ja) * 1983-12-07 1985-07-01 Fujitsu Ltd 半導体装置及びその製造方法
US4578859A (en) * 1984-08-22 1986-04-01 Harris Corporation Implant mask reversal process
US4600445A (en) * 1984-09-14 1986-07-15 International Business Machines Corporation Process for making self aligned field isolation regions in a semiconductor substrate
US4598460A (en) * 1984-12-10 1986-07-08 Solid State Scientific, Inc. Method of making a CMOS EPROM with independently selectable thresholds
US4604790A (en) * 1985-04-01 1986-08-12 Advanced Micro Devices, Inc. Method of fabricating integrated circuit structure having CMOS and bipolar devices
US4725875A (en) * 1985-10-01 1988-02-16 General Electric Co. Memory cell with diodes providing radiation hardness
US4692992A (en) * 1986-06-25 1987-09-15 Rca Corporation Method of forming isolation regions in a semiconductor device
US4717683A (en) * 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US4883767A (en) * 1986-12-05 1989-11-28 General Electric Company Method of fabricating self aligned semiconductor devices
US5292671A (en) * 1987-10-08 1994-03-08 Matsushita Electric Industrial, Co., Ltd. Method of manufacture for semiconductor device by forming deep and shallow regions
US5192993A (en) * 1988-09-27 1993-03-09 Kabushiki Kaisha Toshiba Semiconductor device having improved element isolation area
FR2672732B1 (fr) * 1991-02-12 1997-03-21 Sgs Thomson Microelectronics Structure monolithique comprenant deux ensembles de diodes de protection bidirectionnelles.
JPH05267604A (ja) * 1991-05-08 1993-10-15 Seiko Instr Inc 半導体装置の製造方法
KR0138234B1 (ko) * 1994-02-24 1998-04-28 김광호 고전압 모오스 트랜지스터의 구조
US5982012A (en) * 1998-01-14 1999-11-09 Foveon, Inc. Pixel cells and pixel cell arrays having low leakage and improved performance characteristics
JP3621303B2 (ja) 1999-08-30 2005-02-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US7049669B2 (en) * 2003-09-15 2006-05-23 Infineon Technologies Ag LDMOS transistor
RU2528574C1 (ru) * 2013-03-12 2014-09-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" Способ изготовления изолирующих областей полупроводникового прибора
TWI588918B (zh) * 2014-04-01 2017-06-21 亞太優勢微系統股份有限公司 具精確間隙機電晶圓結構與及其製作方法
CN112447776A (zh) * 2019-08-28 2021-03-05 天津大学青岛海洋技术研究院 一种降低电荷回流的cmos图像传感器像素制作方法
US11342625B2 (en) * 2019-11-04 2022-05-24 Xnrgi, Inc. Method of fabricating and method of using porous wafer battery

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983620A (en) * 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
JPS52131483A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Mis-type semiconductor device
US4135955A (en) * 1977-09-21 1979-01-23 Harris Corporation Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation
US4131907A (en) * 1977-09-28 1978-12-26 Ouyang Paul H Short-channel V-groove complementary MOS device
JPS5529116A (en) * 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
JPS5691461A (en) * 1979-12-25 1981-07-24 Fujitsu Ltd Manufacturing of complementary mos integrated circuit
JPS56118367A (en) * 1980-02-22 1981-09-17 Fujitsu Ltd Preparation of semiconductor device
US4282648A (en) * 1980-03-24 1981-08-11 Intel Corporation CMOS process
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
JPS5817655A (ja) * 1981-07-24 1983-02-01 Hitachi Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
NL188607C (nl) 1992-08-03
NL188607B (nl) 1992-03-02
IT8220661A0 (it) 1982-04-08
US4468852A (en) 1984-09-04
DE3312720C2 (it) 1992-09-17
JPH0479142B2 (it) 1992-12-15
JPS58202562A (ja) 1983-11-25
FR2525030B1 (fr) 1986-04-25
GB2120844A (en) 1983-12-07
DE3312720A1 (de) 1983-10-13
FR2525030A1 (fr) 1983-10-14
GB2120844B (en) 1985-09-25
NL8301229A (nl) 1983-11-01

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Effective date: 19970429