NL188607C - Werkwijze voor het vormen van een stel complementaire mos transistoren. - Google Patents
Werkwijze voor het vormen van een stel complementaire mos transistoren.Info
- Publication number
- NL188607C NL188607C NLAANVRAGE8301229,A NL8301229A NL188607C NL 188607 C NL188607 C NL 188607C NL 8301229 A NL8301229 A NL 8301229A NL 188607 C NL188607 C NL 188607C
- Authority
- NL
- Netherlands
- Prior art keywords
- forming
- mos transistors
- complementary mos
- complementary
- transistors
- Prior art date
Links
- 230000000295 complement effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/07—Guard rings and cmos
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT2066182 | 1982-04-08 | ||
IT8220661A IT1210872B (it) | 1982-04-08 | 1982-04-08 | Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate. |
Publications (3)
Publication Number | Publication Date |
---|---|
NL8301229A NL8301229A (nl) | 1983-11-01 |
NL188607B NL188607B (nl) | 1992-03-02 |
NL188607C true NL188607C (nl) | 1992-08-03 |
Family
ID=11170208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NLAANVRAGE8301229,A NL188607C (nl) | 1982-04-08 | 1983-04-07 | Werkwijze voor het vormen van een stel complementaire mos transistoren. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4468852A (xx) |
JP (1) | JPS58202562A (xx) |
DE (1) | DE3312720A1 (xx) |
FR (1) | FR2525030B1 (xx) |
GB (1) | GB2120844B (xx) |
IT (1) | IT1210872B (xx) |
NL (1) | NL188607C (xx) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4412375A (en) * | 1982-06-10 | 1983-11-01 | Intel Corporation | Method for fabricating CMOS devices with guardband |
JPS60123055A (ja) * | 1983-12-07 | 1985-07-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US4578859A (en) * | 1984-08-22 | 1986-04-01 | Harris Corporation | Implant mask reversal process |
US4600445A (en) * | 1984-09-14 | 1986-07-15 | International Business Machines Corporation | Process for making self aligned field isolation regions in a semiconductor substrate |
US4598460A (en) * | 1984-12-10 | 1986-07-08 | Solid State Scientific, Inc. | Method of making a CMOS EPROM with independently selectable thresholds |
US4604790A (en) * | 1985-04-01 | 1986-08-12 | Advanced Micro Devices, Inc. | Method of fabricating integrated circuit structure having CMOS and bipolar devices |
US4725875A (en) * | 1985-10-01 | 1988-02-16 | General Electric Co. | Memory cell with diodes providing radiation hardness |
US4692992A (en) * | 1986-06-25 | 1987-09-15 | Rca Corporation | Method of forming isolation regions in a semiconductor device |
US4717683A (en) * | 1986-09-23 | 1988-01-05 | Motorola Inc. | CMOS process |
US4883767A (en) * | 1986-12-05 | 1989-11-28 | General Electric Company | Method of fabricating self aligned semiconductor devices |
US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
US5192993A (en) * | 1988-09-27 | 1993-03-09 | Kabushiki Kaisha Toshiba | Semiconductor device having improved element isolation area |
FR2672732B1 (fr) * | 1991-02-12 | 1997-03-21 | Sgs Thomson Microelectronics | Structure monolithique comprenant deux ensembles de diodes de protection bidirectionnelles. |
JPH05267604A (ja) * | 1991-05-08 | 1993-10-15 | Seiko Instr Inc | 半導体装置の製造方法 |
KR0138234B1 (ko) * | 1994-02-24 | 1998-04-28 | 김광호 | 고전압 모오스 트랜지스터의 구조 |
US5982012A (en) * | 1998-01-14 | 1999-11-09 | Foveon, Inc. | Pixel cells and pixel cell arrays having low leakage and improved performance characteristics |
JP3621303B2 (ja) | 1999-08-30 | 2005-02-16 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7049669B2 (en) * | 2003-09-15 | 2006-05-23 | Infineon Technologies Ag | LDMOS transistor |
RU2528574C1 (ru) * | 2013-03-12 | 2014-09-20 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" | Способ изготовления изолирующих областей полупроводникового прибора |
TWI588918B (zh) * | 2014-04-01 | 2017-06-21 | 亞太優勢微系統股份有限公司 | 具精確間隙機電晶圓結構與及其製作方法 |
CN112447776A (zh) * | 2019-08-28 | 2021-03-05 | 天津大学青岛海洋技术研究院 | 一种降低电荷回流的cmos图像传感器像素制作方法 |
US11342625B2 (en) * | 2019-11-04 | 2022-05-24 | Xnrgi, Inc. | Method of fabricating and method of using porous wafer battery |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3983620A (en) * | 1975-05-08 | 1976-10-05 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
JPS5286083A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Production of complimentary isolation gate field effect transistor |
US4013484A (en) * | 1976-02-25 | 1977-03-22 | Intel Corporation | High density CMOS process |
JPS52131483A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Mis-type semiconductor device |
US4135955A (en) * | 1977-09-21 | 1979-01-23 | Harris Corporation | Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation |
US4131907A (en) * | 1977-09-28 | 1978-12-26 | Ouyang Paul H | Short-channel V-groove complementary MOS device |
JPS5529116A (en) * | 1978-08-23 | 1980-03-01 | Hitachi Ltd | Manufacture of complementary misic |
IT1166587B (it) * | 1979-01-22 | 1987-05-05 | Ates Componenti Elettron | Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate |
JPS5691461A (en) * | 1979-12-25 | 1981-07-24 | Fujitsu Ltd | Manufacturing of complementary mos integrated circuit |
JPS56118367A (en) * | 1980-02-22 | 1981-09-17 | Fujitsu Ltd | Preparation of semiconductor device |
US4282648A (en) * | 1980-03-24 | 1981-08-11 | Intel Corporation | CMOS process |
US4391650A (en) * | 1980-12-22 | 1983-07-05 | Ncr Corporation | Method for fabricating improved complementary metal oxide semiconductor devices |
JPS5817655A (ja) * | 1981-07-24 | 1983-02-01 | Hitachi Ltd | 半導体装置の製造方法 |
-
1982
- 1982-04-08 IT IT8220661A patent/IT1210872B/it active
-
1983
- 1983-04-05 US US06/482,156 patent/US4468852A/en not_active Expired - Lifetime
- 1983-04-06 JP JP58059402A patent/JPS58202562A/ja active Granted
- 1983-04-07 NL NLAANVRAGE8301229,A patent/NL188607C/xx active Search and Examination
- 1983-04-08 DE DE19833312720 patent/DE3312720A1/de active Granted
- 1983-04-08 GB GB08309572A patent/GB2120844B/en not_active Expired
- 1983-04-08 FR FR8305752A patent/FR2525030B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
IT8220661A0 (it) | 1982-04-08 |
FR2525030B1 (fr) | 1986-04-25 |
GB2120844B (en) | 1985-09-25 |
FR2525030A1 (fr) | 1983-10-14 |
JPS58202562A (ja) | 1983-11-25 |
DE3312720C2 (xx) | 1992-09-17 |
US4468852A (en) | 1984-09-04 |
DE3312720A1 (de) | 1983-10-13 |
JPH0479142B2 (xx) | 1992-12-15 |
GB2120844A (en) | 1983-12-07 |
IT1210872B (it) | 1989-09-29 |
NL8301229A (nl) | 1983-11-01 |
NL188607B (nl) | 1992-03-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A85 | Still pending on 85-01-01 | ||
BA | A request for search or an international-type search has been filed | ||
BB | A search report has been drawn up | ||
BC | A request for examination has been filed |